XRT79L71 Datasheet, PDF (363/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L71
REV. P1.0.3
BIT NUMBER
NAME
2
Transmit Cell Insertion
Memory Overflow Inter-
rupt Status
1
Detection of HEC Byte
Error Interrupt
0
Detection of Transmit
UTOPIA Parity Error
Interrupt
TYPE
DESCRIPTION
RUR
Transmit Cell Insertion Memory Overflow Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the Trans-
mit Cell Insertion Memory Overflow" Interrupt has occurred since the
last read of this register.
The Transmit ATM Cell Processor block will generate this interrupt
anytime an overflow event has occurred in the "Transmit Cell Inser-
tion Memory" Buffer.
0 - Indicates that the Transmit ATM Cell Processor block has NOT
declared the "Transmit Cell Insertion Memory Overflow" interrupt
since the last read of this register.
1 - Indicates that the Transmit ATM Cell Processor block has
declared the "Transmit Cell Insertion Memory Overflow" interrupt
since the last read of this register.
RUR
Detection of HEC Byte Error Interrupt:
This RESET-upon-READ bit-field indicates whether or not the
"Transmit ATM Cell Processor block" has declared the "Detection of
HEC Byte Error" Interrupt since the last read of this register.
The Transmit ATM Cell Processor block will generate this interrupt
anytime it has received an ATM cell (from the TxFIFO) that contains
a HEC byte error.
0 - Indicates that the Transmit ATM Cell Processor block has NOT
declared the "Detection of HEC Byte Error" Interrupt since the last
read of this register.
1 - Indicates that the Transmit ATM Cell Processor block has
declared the "Detection of HEC Byte Error" Interrupt since the last
read of this register.
Detection of Transmit UTOPIA Parity Error Interrupt:
This RESET-upon-READ bit-field indicates whether or not the
"Transmit ATM Cell Processor" block has declared the "Detection of
Transmit UTOPIA Parity Error" Interrupt since the last read of this
register.
The Transmit ATM Cell Processor block will generate this interrupt
anytime it has received an ATM cell byte or 16-bit word (from the
Transmit UTOPIA Interface block) that contains a parity error.
0 - Indicates that the Transmit ATM Cell Processor block has NOT
declared the "Detection of Transmit UTOPIA Parity Error" Interrupt
since the last read of this register.
1 - Indicates that the Transmit ATM Cell Processor block has
declared the "Detection of Transmit UTOPIA Parity Error" Interrupt
since the last read of this register.
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