XRT79L71 Datasheet, PDF (373/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L71
REV. P1.0.3
TRANSMIT ATM CELL PROCESSOR BLOCK - TRANSMIT ATM IDLE CELL HEADER BYTE 3 (ADDRESS
= 0X1F1A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit Idle Cell Header Byte 3 [7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-0
Transmit Idle Cell
Header Byte - 3 [7:0]
TYPE
DESCRIPTION
R/W Transmit Idle Cell Header Byte - 3[7:0]:
These READ/WRITE register bits, along with that in "Transmit ATM
Cell Processor Block - Transmit ATM Idle Cell Header Bytes 1, 2 and
4" registers permit the user to define the header byte pattern of all Idle
Cells that are generated by the Transmit ATM Cell Processor block.
This register permits the user to define/specify the value of Header
Byte # 3 within each Idle Cell that is generated and transmitted by the
Transmit ATM Cell Processor block.
TRANSMIT ATM CELL PROCESSOR BLOCK - TRANSMIT ATM IDLE CELL HEADER BYTE 4 (ADDRESS
= 0X1F1B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit Idle Cell Header Byte 4 [7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-0
Transmit Idle Cell
Header Byte - 4 [7:0]
TYPE
DESCRIPTION
R/W Transmit Idle Cell Header Byte - 4[7:0]:
These READ/WRITE register bits, along with that in "Transmit ATM
Cell Processor Block - Transmit ATM Idle Cell Header Byte 1 through
Byte 3" registers permit the user to define the header byte pattern of
all Idle Cells that are generated by the Transmit ATM Cell Processor
block.
This register permits the user to define/specify the value of Header
Byte # 4 within each Idle Cell that is generated and transmitted by the
Transmit ATM Cell Processor block.
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