XRT79L71 Datasheet, PDF (43/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

áç
PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L71
REV. P1.0.3
PIN #
A1
B1
H1
K2
L3
NAME
RxGFCClk
RxGFCMSB
RxUClav/RxPPA
RxUClkO/
RxPClkO
RxUClk/
RxPClk
TYPE
O
O
O
O
I
DESCRIPTION
Received GFC Nibble Serial Output Port Clock Signal:
This output pin functions as a part of the Receive GFC Nibble-Field Serial Out-
put Port, also consisting of the RxGFC and RxGFCMSB pins. This pin provides
a clock pulse which allows external circuitry to latch in the GFC Nibble-Data via
the RxGFC output pin.
NOTE: This output pin is only active if the XRT79L71 is operating in the ATM
UNI Mode.
Receive GFC Nibble Field - MSB Indicator:
This output pin functions as a part of the Receive GFC Nibble Field Serial Out-
put port which also consists of the RxGFC and RxGFCClk pins. This pin pulses
"High" the instant that the MSB (Most Significant Bit) of a GFC Nibble is being
output on the RxGFC pin.
NOTE: This output pin is only active if the XRT79L71 is operating in the ATM
UNI Mode.
Receive UTOPIA - Cell Available/Receive POS-PHY Interface - Packet
Available:
The function of this output pin depends upon whether the XRT79L71 has been
configured to operate in the ATM UNI or PPP Mode.
ATM UNI Mode - RxUClav:
The Receive UTOPIA Interface block will assert this output pin in order to indi-
cate that the Rx FIFO has some ATM cell data that needs to be read by the ATM
Layer Processor. This signal is asserted if the RxFIFO contains at least one full
cell of data. This signal toggle "Low" if the RxFIFO is depleted of data, or if it
contains less than one full cell of data.
Multi-PHY Operation:
When the UNI chip is operating in the Multi-PHY mode, this signal will be tri-
stated until the RxClk cycle following the assertion of a valid address on the
Receive UTOPIA Address bus input pins (e.g., if the contents on the Receive
UTOPIA Address bus pins match that with the Receive UTOPIA Address Regis-
ter. Afterwards, this output pin will behave in accordance with the cell-level
handshake mode.
PPP Mode - RxPPA:
The XRT79L71 will drive this output pin "High" whenever a programmable num-
ber of bytes are available to be read from the RxFIFO.
Receive UTOPIA Interface Clock/Receive POS-PHY Interface Clock Out-
put:
This clock output signal is derived from an internal PLL.
Receive UTOPIA Interface Clock Input/Receive POS-PHY Interface Clock
Input:
The function of this input pin depends upon whether the XRT79L71 is operating
in the ATM UNI or PPP Mode.
ATM UNI Mode - RxUClk:
The byte (or word) data, on the Receive UTOPIA Data bus (RxUData[15:0]) is
updated on the rising edge of this signal. The Receive UTOPIA Interface can
be clocked at rates up to 50 MHz.
PPP Mode - RxPClk:
This byte (or word) data, on the Receive POS-PHY Data Bus (RxPData[15:0]) is
updated on the rising edge of this signal. The Receive POS-PHY Interface can
be clocked at rates up to 50MHz.
31