XRT79L71 Datasheet, PDF (154/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

XRT79L71
REV. P1.0.3
PRELIMINARY
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1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
RXE3 INTERRUPT ENABLE REGISTER # 2 - G.751 (DIRECT ADDRESS = 0X1113)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Unused
Change in
FERF State
Interrupt
Enable
Detection of
BIP-4 Error
Interrupt
Enable
Detection of
FAS Bit Error
Interrupt
Enable
R/O
R/O
R/O
R/O
R/W
R/W
R/W
0
0
0
0
0
0
0
BIT 0
Reserved
R/O
0
BIT NUMBER
NAME
7-4
Unused
3
Change in FERF State
Interrupt Enable
2
Detection of BIP-4 Error
Interrupt Enable
1
Detection of FAS Bit Error
Interrupt Enable
0
Unused
TYPE
R/O
R/W
R/W
R/W
R/O
DESCRIPTION
Please set to "0" (the default value) for normal operation
Change in FERF Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the "Change in FERF Condition" Interrupt. If the user
enables this interrupt, then the Frame Synchronizer block will
generate an interrupt anytime the state of the FERF condition
changes.
0 - Disables the "Change in FERF Condition" Interrupt.
1 - Enables the "Change in FERF Condition" Interrupt.
NOTE: This bit-field is ignored anytime the Frame Synchronizer
block is by-passed.
Detection of BIP-4 Error Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the "Detection of BIP-4 Error" Interrupt. If the user
enables this interrupt, then the Frame Synchronizer block will
generate an interrupt anytime it detects a BIP-4 error, within the
incoming E3 data stream.
0 - Disables the "Detection of BIP-4 Error" Interrupt.
1 - Enables the "Detection of BIP-4 Error" Interrupt.
NOTE: This bit-field is ignored anytime the Frame Synchronizer
block is by-passed.
Detection of FAS (Framing Alignment Signal) Bit Error Inter-
rupt Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the "FAS Bit Error" Interrupt. If the user enables this
interrupt, then the Frame Synchronizer block will generate an
interrupt anytime it detects an FAS error within the incoming E3
data stream.
0 - Disables the "Detection of FAS Bit Error" Interrupt.
1 - Enables the "Detection of FAS Bit Error" Interrrupt.
NOTE: This bit-field is ignored if the Frame Synchronizer block is
by-passed.
Please set to "0" (the default value) for normal operation.
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