XRT79L71 Datasheet, PDF (284/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

XRT79L71
REV. P1.0.3
PRELIMINARY
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1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE ATM CELL COUNT REGISTER - BYTE 3
(ADDRESS = 0X1728)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive ATM Cell Count[31:24]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-0
Receive ATM Cell
Count[31:24]
TYPE
RUR
DESCRIPTION
Receive ATM Cell Count [31:24]:
These RESET-upon-READ bit-fields, along with that within the
"Receive ATM Cell Processor Block - Receive ATM Cell Count
Registers - Bytes 2 through 0" contain the 32-bit expression for
the number of cells that has been received by the Receive FIFO
(e.g., where it can be read out via the Receive UTOPIA Interface
Block) since the last read of these registers.
This particular register byte contains the MSB (Most Significant
Byte) of this 32-bit value for the number of Received ATM cells.
NOTES:
1. The contents within these register bytes do not include
Idle Cells, and Cells that have been discarded due to
uncorrectable HEC byte errors, or those cells that have
been discarded via the User Cell Filter.
2. If the number of Received ATM Cells reaches the value
"0xFFFFFFFF" then these registers will saturate to and
remain at this value (e.g., it will not overflow to
"0x00000000").
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