XRT79L71 Datasheet, PDF (141/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (DIRECT ADDRESS = 0X1117)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Unused
FEAC
Valid
RxFEAC
Remove
Interrupt
Enable
RxFEAC
Remove
Interrupt
Status
RxFEAC
Valid
Interrupt
Enable
R/O
R/O
R/O
R/O
R/W
RUR
R/W
0
0
0
0
0
0
0
XRT79L71
REV. P1.0.3
BIT 0
RxFEAC
Valid
Interrupt
Status
RUR
0
BIT NUMBER
NAME
7-5
Unused
4
FEAC Valid
3
RxFEAC Remove
Interrupt Enable
2
RxFEAC Remove
Interrupt Status
1
RxFEAC Valid Interrupt
Enable
TYPE
R/O
R/O
R/W
RUR
R/W
DESCRIPTION
Please set to "0" (the default value) for normal operation.
FEAC Message Validation Indicator:
This READ-ONLY bit-field indicates that the FEAC Code (which
resides within the "RxDS3 FEAC" Register) has been validated
by the Receive FEAC Controller. The Receive FEAC Controller
will validate a FEAC codeword if it has received this codeword in
8 out of the last 10 FEAC Messages. Polled systems can moni-
tor this bit-field, when checking for a newly validated FEAC code-
word.
0 - FEAC Message is not (or no longer) validated.
1 - FEAC Message has been validated.
FEAC Message Remove Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the "Receive FEAC Remove Interrupt". If the user
enables this interrupt, then the Framer Synchronizer will gener-
ate an interrupt anytime the most recently validated FEAC Mes-
sage has been removed. The Receive FEAC Controller will
remove a validated FEAC codeword, if it has received a different
codeword in 3 out of the last 10 FEAC Messages.
0 - Receive FEAC Remove Interrupt is disabled.
1 - Receive FEAC Remove Interrupt is enabled.
NOTE: This bit-field is ignored if the Frame Synchronizer block is
by-passed.
FEAC Message Remove Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
"FEAC Message Remove Interrupt" has occurred since the last
read of this register.
0 - FEAC Message Remove Interrupt has NOT occurred since
the last read of this register.
1 - FEAC Message Remove Interrupt has occurred since the last
read of this register.
FEAC Message Validation Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the FEAC Message Validation Interrupt. If the user
enables this interrupt, then the Frame Synchronizer block will
generate an interrupt anytime a new FEAC Codeword has been
validated by the Receive FEAC Controller.
0 - FEAC Message Validation Interrupt is NOT enabled.
1 - FEAC Message Validation Interrupt is enabled.
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