XRT79L71 Datasheet, PDF (124/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

XRT79L71
REV. P1.0.3
BIT NUMBER
NAME
4
RESET
3
Interrupt Enable RESET
2
Frame Format
PRELIMINARY
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1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
TYPE
R/W
R/W
R/W
DESCRIPTION
Software RESET Input:
A "0" to "1" transition in this bit-field commands a Software
RESET to the Channel. Once the user executes a Software
reset to the frame, all of the internal state machines will be reset;
and the Frame Synchronizer block will execute a "Reframe"
operation.
NOTE: For a Software Reset, the contents of the Command
Register will not be reset to their default values.
Interrupt Enable Reset:
This READ/WRITE bit-field permits the user to configure the
Channel to automatically disable any interrupt following its acti-
vation.
0 - Interrupts are NOT automatically disabled following their acti-
vation.
1 - Interrupt are automatically disabled following their activation.
Frame Format:
This READ/WRITE bit-field, along with Bit 6 (IsDS3), permits the
user to configure the Frame Generator/Frame Synchronizer
block to operate in the appropriate framing format. The relation-
ship between the state of this bit-field, Bit 2 and the resulting
framing format is presented below.
Bit 6 (IsDS3)
0
0
1
1
Bit 2 (Fram e
Form at)
0
1
0
1
Fram ing Form at
E3, ITU-T G.751
E3, ITU-T G.832
DS3, C-bit Parity
DS3, M13
1-0
TimRefSel[1:0]
R/W
Time Reference Select:
These two READ/WRITE bit-fields permit the user to define both
the timing source and the framing-alignment source for the
Frame Generator block, as presented below.
Tim RefSel[1:0]
Tim ing Reference
Loop-Tim ing (Tim ing is
00
taken from the Fram e
Synchronizer block)
Fram ing
Reference
Asynchronous
01
Transm it Clock Source for _{TxDS3FP Input}
the Fram e Generator block
Transm it Clock Source for
10
Asynchronous
the Fram e Generator block
11
Transm it Clock Source for _Asynchronous
the Fram e Generator block
112