XRT79L71 Datasheet, PDF (24/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

XRT79L71
REV. P1.0.3
PIN #
C9
NAME
TxSer
TxPOH
SendMSG
B3
TxPOHClk
PRELIMINARY
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1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
TYPE
DESCRIPTION
I Transmit Payload Data Serial Input/Transmit PLCP Path Overhead Input/
Send HDLC Message Request Input:
The function of this input pin depends upon whether the XRT79L71 is configured
to operate in the Clear-Channel Framer Mode, the High-Speed HDLC Controller
Mode or in the ATM/PLCP Mode.
Clear-Channel Framer Mode - TxSer:
If the XRT79L71 is configured to operate in the Clear-Channel Framer mode,
then this input pin functions as the Transmit Payload Data Serial Input pin. In this
case, the local terminal equipment is expected to apply all outbound data which
is intended to be carried via the DS3 or E3 payload bits to this input pin.
The Transmit Payload Data Input Interface will sample the data, residing at the
TxSer input pin, upon the rising edge of TxInClk.
ATM/PLCP Mode - TxPOH:
If the XRT79L71 is configured to operate in the ATM Mode, and if within the ATM
Mode, the chip is also configured to operate in the PLCP Mode, then this input
pin functions as the Transmit PLCP Path Overhead Input Pin. In this mode, the
user can externally insert desired path overhead byte values into the outbound
PLCP frames.
The Transmit PLCP Path Overhead Input Pin (and Port) become active whenever
the user asserts the TxPOHIns input pin by pulling it "High". In this case, the
data, residing upon the TxPOH input pin will be sampled upon the rising edge of
the TxPOHClk signal.
NOTE: This input pin is inactive if the XRT79L71 is configured to operate in the
Direct-Mapped ATM Mode.
High-Speed HDLC Controller Mode - SendMSG:
If the XRT79L71 is configured to operate in the High-Speed HDLC Controller
Mode, then this input pin functions as the Transmit HDLC Controller Input Inter-
face enable input pin.
If the user asserts this input pin by pulling it "High" then the Transmit HDLC Con-
troller Input Interface will proceed to latch the data, residing on the TxHDL-
CDat[7:0] input pins, upon each rising edge of the TxHDLCClk signal. All data
that is latched into the Transmit HDLC Controller Input Interface for the duration
that the SendMSG input pin is "High" will be encapsulated into an HDLC frame
and ultimately transported via the payload bits of the outbound DS3 or E3 data
stream.
If the user pulling this input pin "Low", then the Transmit HDLC Controller Input
Interface will cease latching the data, residing on the TxHDLCDat[7:0] bus.
NOTE: This input pin is inactive if the XRT79L71 has been configured to operate
in the PPP Mode.
O Transmit PLCP Frame POH Byte Insertion Clock:
This pin, along with the TxPOH and the TxPOHMSB input pins, function as the
Transmit PLCP Frame POH Byte serial input port. This output pin functions as a
clock output signal that is be used to sample the user's POH data at the TxPOH
input pin. This output pin is always active, independent of the state of the TxPO-
HIns pin.
NOTE: This pin is only active if the XRT79L71 has been configured to operate in
the ATM/PLCP Mode.
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