XRT79L71 Datasheet, PDF (265/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L71
REV. P1.0.3
BIT NUMBER
NAME
0
Receive Cell Extraction
Interrupt Status
TYPE
RUR
DESCRIPTION
Receive Cell Extraction Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
"Receive Cell Extraction" Interrupt has occurred since the last
read of this register.
The Receive ATM Cell Processor block will generate the
"Receive Cell Extraction" Interrupt anytime it receives an incom-
ing ATM cell (from traffic) and loads an ATM cell into the "Extrac-
tion Memory" Buffer.
0 - Indicates that the "Receive Cell Extraction" Interrupt has NOT
occurred since the last read of this register.
1 - Indicates that the "Receive Cell Extraction" Interrupt has
occurred since the last read of this register.
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE ATM INTERRUPT STATUS REGISTER - BYTE 0
(ADDRESS = 0X170B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive Cell
Insertion
Interrupt
Status
Receive FIFO
Overflow
Interrupt
Status
Receive Cell
Extraction
Memory
Overflow
Interrupt
Status
Receive Cell Detection of
Insertion Correctable
Memory
HEC Byte
Overflow Error Interrupt
Interrupt
Status
Status
Detection of
Uncorrect-
able HEC
Byte Error
Interrupt
Status
Clearance of Declaration of
LCD Interrupt LCD Interrupt
Status
Status
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7
Receive Cell Insertion
Interrupt Status
6
Receive FIFO Overflow
Interrupt Status
TYPE
RUR
RUR
DESCRIPTION
Receive Cell Insertion Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
"Receive Cell Insertion" Interrupt has occurred since the last
read of this register.
The Receive ATM Cell Processor block will generate the
"Receive Cell Insertion" Interrupt anytime a cell (residing in the
Receive Cell Insertion Buffer) is read out of the "Receive Cell
Insertion Buffer and is loaded into the incoming ATM cell traffic.
0 - Indicates that the "Receive Cell Insertion" Interrupt has NOT
occurred since the last read of this register.
1 - Indicates that the "Receive Cell Insertion" Interrupt has
occurred since the last read of this register.
Receive FIFO Overflow Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
"Receive FIFO Overflow" Interrupt has occurred since the last
read of this register.
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