XRT79L71 Datasheet, PDF (301/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L71
REV. P1.0.3
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 0 - PATTERN REGISTER -
HEADER BYTE 4 (ADDRESS = 0X1747)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive User Cell Filter # 0 - Pattern Register - Byte 4 [7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-0
Receive User Cell Filter #
0 - Pattern Register -
Header Byte 4
TYPE
DESCRIPTION
R/W Receive User Cell Filter # 0 - Pattern Register - Header Byte 4:
The User Cell filtering criteria (for Receive User Cell Filter # 0) is
defined based upon the contents of 9 read/write registers. These
registers are the four "Receive ATM Cell Processor Block - Receive
User Cell Filter # 0 - Pattern Registers", the four "Receive ATM Cell
Processor Block - Receive User Cell Filter # 0 - Check Registers"
and the "Receive ATM Cell Processor Block - Receive User Cell Fil-
ter # 0 Control Register.
This READ/WRITE register, along with the "Receive ATM Cell Pro-
cessor Block - Receive User Cell Filter # 0 - Check Register -
Header Byte 4" permits the user to define the User Cell Filtering cri-
teria for "Octet # 4" of the incoming User Cell. The user will write
the header byte pattern (for Octet 4) that he/she wishes to use as
part of the "User Cell Filtering" criteria, into this register. The user
will also write in a value into the "Receive ATM Cell Processor Block
- Receive User Cell Filter # 0 - Check Register - Header Byte 4"
that indicates which bits within the first octet of the incoming cells
are to be compared with the contents of this register.
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