XRT79L71 Datasheet, PDF (382/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

XRT79L71
REV. P1.0.3
PRELIMINARY
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1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
TRANSMIT ATM CELL PROCESSOR BLOCK - TRANSMIT ATM HEC BYTE ERROR COUNT REGISTER -
BYTE 1 (ADDRESS = 0X1F32)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit - HEC Byte Error Count[15:8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-0
Transmit - HEC Byte
Error Count[15:8]
TYPE
DESCRIPTION
RUR
Transmit - HEC Byte Error Count - Byte 1[7:0]:
This RESET-upon-READ register, along with the "Transmit ATM Cell
Processor Block - Transmit ATM HEC Byte Error Count Register -
Bytes 3, 2 and 0" register, contain a 32-bit value for the number of
ATM cells that contain HEC byte errors (as detected by the Transmit
ATM Cell Processor block).
NOTES:
1. This register is valid if the Transmit ATM Cell Processor block
has been configured to compute and verify the HEC byte of
each ATM cell that it receives from the TxFIFO or the
"Transmit Cell Insertion Buffer".
2. If the number of cells reaches the value "0xFFFFFFFF", then
these registers will saturate to and remain at this value (e.g.,
it will NOT overflow to "0x00000000").
TRANSMIT ATM CELL PROCESSOR BLOCK - TRANSMIT ATM HEC BYTE ERROR COUNT REGISTER -
BYTE 0 (ADDRESS = 0X1F33)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit - HEC Byte Error Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-0
Transmit - HEC Byte
Error Count[7:0]
TYPE
DESCRIPTION
RUR
Transmit - HEC Byte Error Count - Byte 0[7:0]:
This RESET-upon-READ register, along with the "Transmit ATM Cell
Processor Block - Transmit ATM HEC Byte Error Count Register -
Bytes 3 through 1" register, contain a 32-bit value for the number of
ATM cells that contain HEC byte errors (as detected by the Transmit
ATM Cell Processor block).This particular register functions as the
LSB (Least Significant Byte) for this 32-bit expression.
NOTES:
1. This register is valid if the Transmit ATM Cell Processor block
has been configured to compute and verify the HEC byte of
each ATM cell that it receives from the TxFIFO or the
"Transmit Cell Insertion Buffer".
2. If the number of cells reaches the value "0xFFFFFFFF", then
these registers will saturate to and remain at this value (e.g.,
it will NOT overflow to "0x00000000").
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