XRT79L71 Datasheet, PDF (269/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L71
REV. P1.0.3
BIT NUMBER
NAME
4
Receive Cell Insertion
Memory Overflow Inter-
rupt Enable
3
Detection of Correctable
HEC Byte Error Interrupt
Enable
2
Detection of Uncorrect-
able HEC Byte Error
Interrupt Enable
1
OCD?
0
LCD
TYPE
R/W
R/W
R/W
R/W
R/W
DESCRIPTION
Receive Cell Insertion Memory Overflow Interrupt Enable:This
READ/WRITE bit-field permits the user to either enable or dis-
able the "Receive Cell Insertion Memory Overflow" Interrupt.
If the user enables this interrupt, then the Receive ATM Cell Pro-
cessor block will generate an interrupt any time an overflow
event has occurred in the "Receive Cell Insertion Memory"
buffer.
0 - Disables the Receive Cell Insertion Memory Overflow Inter-
rupt.
1 - Enables the Receive Cell Insertion Memory Overflow Inter-
rupt.
Detection of Correctable HEC Byte Error Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the "Detection of Correctable HEC Byte Error Interrupt"
within the Receive ATM Cell Processor block.
If the user enables this interrupt, then the Receive ATM Cell Pro-
cessor block will generate an interrupt each time it receives an
ATM cell (in incoming traffic) that contains a "correctable" HEC
Byte error.
0 - Disables the "Detection of Correctable HEC Byte Error" Inter-
rupt.
1 - Enables the "Detection of Correctable HEC Byte Error" Inter-
rupt.
Detection of Uncorrectable HEC Byte Error Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the "Detection of Uncorrectable HEC Byte Error" Inter-
rupt within the Receive ATM Cell Processor block.
If the user enables this interrupt, then the Receive ATM Cell Pro-
cessor block will generate an interrupt each time it receives an
ATM cell (in incoming traffic) that contains an "uncorrectable"
HEC Byte error.
0 - Disables the "Detection of Uncorrectable HEC Byte Error"
Interrupt.
1 - Enables the "Detection of Uncorrectable HEC Byte Error"
Interrupt.
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE ATM CELL INSERTION/EXTRACTION MEMORY
CONTROL REGISTER (ADDRESS = 0X1713)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Receive Cell
Extraction
Memory
RESET*
Receive Cell
Extraction
Memory
CLAV
Receive Cell
Insertion
Memory
RESET*
Receive Cell
Insertion
Memory
ROOM
Receive Cell
Insertion
Memory
WSOC
R/O
R/O
R/O
R/W
R/O
R/W
R/O
W/O
0
0
0
1
0
1
0
0
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