XRT79L71 Datasheet, PDF (189/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L71
REV. P1.0.3
TXDS3 FEAC CONFIGURATION AND STATUS REGISTER (DIRECT ADDRESS = 0X1131)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Unused
TxFEAC
Interrupt
Enable
TxFEAC
Interrupt
Status
TxFEAC
Enable
TxFEAC
Go
R/O
R/O
R/O
R/W
RUR
R/W
R/W
0
0
0
0
0
0
0
BIT 0
TxFEAC
Busy
R/O
0
BIT NUMBER
NAME
7-5
Unused
4
TxFEAC Interrupt Enable
3
TxFEAC Interrupt Status
2
TxFEAC Enable
1
TxFEAC Go
TYPE
R/O
R/W
RUR
R/W
R/W
DESCRIPTION
Please set to "0" for normal operation.
Transmit FEAC Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the "Transmit FEAC" Interrupt. If the user enables this
interrupt, then the Frame Generator will generate an interrupt,
once it has completed its 10th transmission of a given FEAC
Message to the remote terminal equipment.
0 - Transmit FEAC Interrupt is disabled.The Frame Generator
block will NOT generate an interrupt after it has completed its
10th transmission of a given FEAC Message.
1 - Transmit FEAC Interrupt is enabled.The Frame Generator
block will generate an interrupt after it has completed its 10th
transmission of a given FEAC Message.
Transmit FEAC Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
"Transmit FEAC Interrupt" has occurred since the last read of
this register.
0 - The Transmit FEAC Interrupt has NOT occurred since the last
read of this register.
1 - The Transmit FEAC Interrupt has occurred since the last read
of this register.
Transmit FEAC Controller Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the Transmit FEAC Controller, within the Frame Genera-
tor block.
0 - Disables the Transmit FEAC Controller.
1 - Enables the Transmit FEAC Controller.
Transmit FEAC Message Command:
A "0" to "1" transition, within this bit-field configures the Transmit
FEAC Controller to begin its transmission of the FEAC Message
(which consists of the FEAC code, as specified within the
"TxDS3 FEAC" Register).
NOTE: The user is advised to perform a write operation that
resets this bit-field back to "0", following execution of the
command to transmit a FEAC Message.
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