XRT79L71 Datasheet, PDF (41/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L71
REV. P1.0.3
PIN #
A6
C4
NAME
RxPOH_Clk/
RxClk/
RxNibClk
RxPOHFrame
TYPE
O
O
DESCRIPTION
Receive PLCP Path Overhead Serial Port Clock output/Receive Nibble-Par-
allel Output port clock/Receive Serial Clock output:
The function of this output pin depends upon whether the XRT79L71 has been
configured to operate in the ATM/PLCP Mode or the Clear-Channel Framer
Mode.
ATM/PLCP Mode - RxPOH_Clk:
This output clock pin along with RxPOH, RxPOHFrame and RxPOHIns pins
comprise the Receive PLCP Frame POH Byte serial output port. All POH (Path
Overhead) data that is output via the RxPOH output pin is updated on the rising
edge of this clock signal.
NOTE: This output signal is inactive if the XRT79L71 has been configured to
operate in the Direct-Mapped ATM Mode.
Clear-Channel Framer Mode - RxClk:
This output pin is active whenever the XRT79L71 has been configured to oper-
ate in either the Serial or Nibble Parallel Mode, as is described below.Clear-
Channel Framer/Serial Mode - RxClkIn this serial mode, this output is a
44.736MHz clock output signal (for DS3 applications) or 34.368MHz clock out-
put signal (for E3 applications). The Receive Payload Data Output Interface will
update the data via the RxSer output pin, upon the rising edge of this clock sig-
nal.
The user is advised to design (or configure) the local terminal equipment to
sample the RxSer data, upon the falling edge of this clock signal.
Clear-Channel Framer/Nibble-Parallel Mode - RxNibClk:
In the Nibble-Parallel Mode, the XRT79L71 will derive this clock signal from the
RxLineClk signal. The XRT79L71 will pulse this clock signal 1176 times for
each inbound DS3 frame or 1074 times for each inbound E3/ITU-T G.832 frame
or 384 times for each inbound E3/ITU-T G.751 frame. The Receive Payload
Data Output Interface block will update the data on the RxNib[3:0] output upon
the falling edge of this clock signal.
The user is advised to design (or configure) the local terminal equipment to
sample the data on the RxNib[3:0] output pins, upon the rising edge of this clock
signal.
Receive PLCP Frame POH Serial Output Port - Frame Indicator:
This output pin along with the RxPOH RxPOHClk and RxPOHIns pins comprise
the Receive PLCP Frame POH Byte serial output port. This output pin provides
framing information to external circuitry receiving and processing this POH
(Path Overhead) data, by pulsing "High" whenever the first bit of the Z6 byte is
being output via the RxPOH output pin. This pin is "Low" at all other times dur-
ing this PLCP POH Framing cycle.
NOTE: This output pin is only active if the XRT79L71 has been configured to
operate in the ATM/PLCP Modes.
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