XRT79L71 Datasheet, PDF (26/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

XRT79L71
REV. P1.0.3
PIN #
D9
NAME
TxNibClk/
TxGFCMSB/
SendFCS
PRELIMINARY
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1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
TYPE
DESCRIPTION
I/O Transmit Nibble Clock Output pin/Transmit GFC Byte - MSB Indicator Out-
put/Send FCS Value Request Input:
The function of this input/output pin depends upon whether the XRT79L71 is
configured to operate in the Clear-Channel Framer Mode, the High-Speed HDLC
Controller Mode or in the ATM Mode.
Clear-Channel Framer Mode - TxNibClk:
When operating in the Nibble-Parallel Mode the XRT79L71 will derive this clock
signal from either the TxInClk or the RxLineClk signal depending upon whether
the chip is operating in the Local-Timing or Loop-Timing Mode.
The user is advised to configure the Terminal Equipment to output the outbound
payload data to the XRT79L71 onto the TxNib_[3:0] input pins, upon the rising
edge of this clock signal. The Transmit Payload Data Input Interface block will
sample the data, residing on the TxNib_[3:0] line, upon the falling edge this clock
signal.
NOTES:
1. For DS3 applications, the XRT79L71 will output 1176 clock pulses to
the local terminal equipment for each outbound DS3 frame.
2. For E3, ITU-T G.832 applications, the XRT79L71 will output 1074 clock
pulses to the local terminal equipment for each outbound E3 frame.
3. For E3, ITU-T G.751 applications, the XRT79L71 will output 384 clock
pulses to the local terminal equipment for each outbound E3 frame.
ATM Mode - TxGFCMSB:
This signal, along with TxGFC and TxGFCClk combine to function as the Trans-
mit GFC Nibble Field serial input port. This output signal will pulse "High" when
the MSB (most significant bit) of the GFC nibble for a given outbound cell is
expected at the TxGFC input pin.
High-Speed HDLC Controller Mode - SendFCS:
The local terminal equipment is expected to control both this input pin, along with
the SendMSG input pin, during the construction and transmission of each out-
bound HDLC frame.
This input pin is used to command the Transmit HDLC Controller block to com-
pute and insert the computed FCS (Frame-Check Sequence) value into the
back-end of the outbound HDLC frame, as a trailer.
If the user has configured the Transmit HDLC Controller block to compute and
insert a CRC-16 value into the outbound HDLC frame, then the local terminal
equipment is expected to hold this input pin "High" for two periods of TxHDL-
CClk.Conversely, if the user has configured the Transmit HDLC Controller block
to compute and insert a CRC-32 value into the outbound HDLC frame, then the
local terminal equipment is expected to hold this input pin "High" for four (4) peri-
ods of TxHDLCClk.
NOTES:
1. This input/output pin is inactive if the XRT79L71 has been configured to
operate in the PPP Mode.
2. This input/output pin is inactive if the XRT79L71 has been configured to
operate in the Clear-Channel Framer/Serial mode.
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