XRT79L71 Datasheet, PDF (266/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

XRT79L71
REV. P1.0.3
BIT NUMBER
NAME
5
Receive Cell Extraction
Memory Overflow Inter-
rupt Status
4
Receive Cell Insertion
Memory Overflow Inter-
rupt Status
3
Detection of Correctable
HEC Byte Error Interrupt
Status
PRELIMINARY
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1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
TYPE
RUR
RUR
RUR
DESCRIPTION
Receive Cell Extraction Memory Overflow Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
"Receive Cell Extraction Memory Overflow" Interrupt has
occurred since the last read of this register.
The Receive ATM Cell Processor block will generate this inter-
rupt anytime an overflow event has occurred in the "Receive Cell
Extraction Memory" Buffer.
0 - Indicates that the Receive ATM Cell Processor block has
NOT declared the "Receive Cell Extraction Memory Overflow"
Interrupt since the last read of this register.
1 - Indicates that the Receive ATM Cell Processor block has
declared the "Receive Cell Extraction Memory Overflow" inter-
rupt since the last read of this register.
Receive Cell Insertion Memory Overflow Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
"Receive Cell Insertion Memory Overflow" Interrupt has occurred
since the last read of this register.
The Receive ATM Cell Processor block will generate this inter-
rupt anytime an overflow event has occurred in the "Receive Cell
Insertion Memory" Buffer.
0 - Indicates that the Receive ATM Cell Processor block has
NOT declared the "Receive Cell Insertion Memory Overflow"
interrupt since the last read of this register.
1 - Indicates that the Receive ATM Cell Processor block has
declared the "Receive Cell Insertion Memory Overflow" interrupt
since the last read of this register.
Detection of Correctable HEC Byte Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
"Receive ATM Cell Processor block" has declared the "Detection
of Correctable HEC Byte Error" interrupt since the last read of
this register.
The Receive ATM Cell Processor block will generate this inter-
rupt anytime it has received an ATM cell that contains a "correct-
able" HEC byte error.
0 - Indicates that the Receive ATM Cell Processor block has
NOT declared the "Detection of Correctable HEC Byte Error"
Interrupt since the last read of this register.
1 - Indicates that the Receive ATM Cell Processor block has
declared the "Detection of Correctable HEC Byte Error" Interrupt
since the last read of this register.
254