XRT79L71 Datasheet, PDF (326/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

XRT79L71
REV. P1.0.3
PRELIMINARY
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1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 2 - PATTERN REGISTER -
HEADER BYTE 2 (ADDRESS = 0X1765)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
User Cell Filter # 2 - Pattern Register - Byte 2 [7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-0
User Cell Filter # 0 - Pat-
tern Register - Header
Byte 2
TYPE
R/W
DESCRIPTION
User Cell Filter # 2 - Pattern Register - Header Byte 2:
The User Cell filtering criteria (for User Cell Filter # 2) is defined
based upon the contents of 9 read/write registers. These regis-
ters are the four "Receive ATM Cell Processor Block - Receive
User Cell Filter # 2 - Pattern Registers", the four "Receive ATM
Cell Processor Block - Receive User Cell Filter # 2 - Check Reg-
isters" and the "Receive ATM Cell Processor Block - Receive
User Cell Filter # 2 Control Register.
This READ/WRITE register, along with the "Receive ATM Cell
Processor Block - Receive User Cell Filter # 2 - Check Register -
Header Byte 2" permits the user to define the User Cell Filtering
criteria for "Octet # 2" of the incoming User Cell. The user will
write the header byte pattern (for Octet 2) that he/she wishes to
use as part of the "User Cell Filtering" criteria, into this register.
The user will also write in a value into the "Receive ATM Cell
Processor Block - Receive User Cell Filter # 2 - Check Register -
Header Byte 2" that indicates which bits within the first octet of
the incoming cells are to be compared with the contents of this
register.
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