XRT79L71 Datasheet, PDF (138/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

XRT79L71
REV. P1.0.3
BIT NUMBER
NAME
4
Change of Idle Condition
Interrupt Status
3
Change of FERF Condi-
tion Interrupt Status
2
Change of AIC State
Interrupt Status
1
Change of OOF Condi-
tion Interrupt Status
0
Detection of P-Bit Error
Interrupt Status
PRELIMINARY
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1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
TYPE
RUR
RUR
RUR
RUR
RUR
DESCRIPTION
Change in Idle Condition Interrupt Status:
This RESET-upon-READ register indicates whether or not the
"Change in Idle Condition" interrupt has occurred since the last
read of this register.
0 - The "Change in Idle Condition" Interrupt has not occurred
since the last read of this register.
1 - The "Change in Idle Condition" Interrupt has occurred since
the last read of this register.
NOTE: This bit-field is ignored if the Frame Synchronizer block is
by-passed.
Change in FERF Condition Interrupt Status:
This RESET-upon-READ register indicates whether or not the
"Change in FERF Condition" Interrupt has occurred since the
last read of this register.
0 - The "Change in FERF Condition" Interrupt has not occurred
since the last read of this register.
1 - The "Change in FERF Condition" Interrupt has occurred
since the last read of this register.
NOTE: This bit-field is ignored if the Frame Synchronizer block is
by-passed.
Change in AIC State Interrupt Status:
This RESET-upon-READ register bit indicates whether or not the
"Change in AIC State" interrupt has occurred since the last read
of this register.
0 - The "Change in AIC State" Interrupt has not occurred since
the last read of this register.
1 - The "Change in AIC State" Interrupt has occurred since the
last read of this register.
NOTE: This bit-field is ignored if the Frame Synchronizer block is
by-passed.
Change in OOF Condition Interrupt Status:
This RESET-upon-READ register indicates whether or not the
"Change in OOF Condition" Interrupt has occurred since the last
read of this register.
0 - The "Change in OOF Condition" Interrupt has not occurred
since the last read of this register.
1 - The "Change in OOF Condition" Interrupt has occurred since
the last read of this register.
NOTE: This bit-field is ignored if the Frame Synchronizer block is
by-passed.
Detection of P-Bit Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
"Detection of CP-Bit Error" Interrupt has occurred since the last
read of this register.
0 - The "Detection of CP-Bit Error" Interrupt has not occurred
since the last read of this register.
1 - The "Detection of CP-Bit Error" Interrupt has occurred since
the last read of this register.
NOTE: This bit-field is ignored if the Frame Synchronizer block is
by-passed.
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