XRT79L71 Datasheet, PDF (5/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L71
REV. P1.0.3
E3 LINE SIDE PARAMETERS ......................................................................................................................... 46
FIGURE 10. PULSE MASK FOR E3 (34.368MBPS) INTERFACE AS PER ITU-T G.703 ......................................................................... 46
TABLE 7: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS ....................................................... 46
DS3 LINE SIDE PARAMETERS ...................................................................................................................... 47
FIGURE 11. BELLCORE GR-499-CORE PULSE TEMPLATE REQUIREMENTS FOR DS3 APPLICATIONS................................................ 47
TABLE 8: DS3 PULSE MASK EQUATIONS ........................................................................................................................................ 48
TABLE 9: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) ................................. 48
TRANSMIT UTOPIA INTERFACE ................................................................................... 49
FIGURE 12. TIMING DIAGRAM FOR THE TRANSMIT UTOPIA INTERFACE BLOCK ................................................................................ 49
TABLE 10: TIMING INFORMATION FOR THE TRANSMIT UTOPIA INTERFACE BLOCK ........................................................................... 49
TRANSMIT PAYLOAD DATA INPUT INTERFACE ........................................................ 50
TRANSMIT PAYLOAD DATA INPUT INTERFACE - TIMING REQUIREMENTS..................................... 50
TABLE 11: TIMING INFORMATION FO RTHE TRNASMIT PAYLOAD DATA INPUT INTERFACE BLOCK ........................................................ 50
FIGURE 13. TIMING DIAGRAM FOR THE TRANSMIT PAYLOAD DATA INPUT INTERFACE WHEN THE XRT79L71 IS OPERATING IN BOTH THE DS3
AND LOOP-TIMING MODES .............................................................................................................................................. 51
FIGURE 14. TIMING DIAGRAM FOR THE TRANSMIT PAYLOAD DATA INPUT INTERFACE WHEN THE XRT79L71 IS OPERATING IN BOTH THE DS3
AND LOCAL-TIMING MODES............................................................................................................................................. 52
FIGURE 15. TIMING DIAGRAM FOR THE TRANSMIT PAYLOAD DATA INPUT INTERFACE WHEN THE XRT79L71 IS OPERATING IN BOTH THE DS3/
NIBBLE-PARALLEL AND LOOP-TIMING MODES .................................................................................................................. 52
FIGURE 16. TIMING DIAGRAM FOR THE TRANSMIT PAYLOAD DATA INPUT INTERFACE WHEN THE XRT79L71 IS OPERATING IN BOTH THE DS3/
NIBBLE-PARALLEL AND LOCAL-TIMING MODES................................................................................................................. 53
TRANSMIT OVERHEAD DATA INPUT INTERFACE...................................................... 54
TRANSMIT OVERHEAD DATA INPUT INTERFACE - TIMING REQUIREMENTS.................................. 54
TABLE 12: TIMING INFORMATION FOR THE TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK ..................................................... 54
FIGURE 17. TIMING DIAGRAM FOR THE TRANSMIT OVERHEAD DATA INPUT INTERFACE (METHOD 1 ACCESS) .................................... 56
FIGURE 18. TIMING DIAGRAM FOR THE TRANSMIT OVERHEAD DATA INPUT INTERFACE (METHOD 2 ACCESS) .................................... 56
RECEIVE PAYLOAD DATA OUTPUT INTERFACE ....................................................... 57
RECEIVE PAYLOAD DATA OUTPUT INTERFACE - TIMING REQUIREMENTS ................................... 57
TABLE 13: TIMING INFORMATION FOR THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK ...................................................... 57
FIGURE 19. TIMING DIAGRAM FOR THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE (SERIAL MODE).............................................. 57
FIGURE 20. TIMING DIAGRAM FOR THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE (NIBBLE-PARALLEL MODE) ............................. 58
RECEIVE OVERHEAD DATA OUTPUT INTERFACE .................................................... 59
RECEIVE OVERHEAD DATA OUTPUT INTERFACE - TIMING REQUIREMENTS ................................ 59
AC ELECTRICAL CHARACTERISTICS (CONT.)................................................................................................. 59
FIGURE 21. TIMING DIAGRAM FOR THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE (METHOD 1 - USING RXOHCLK) .................. 60
FIGURE 22. TIMING DIAGRAM FOR THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE (METHOD 2 - USING RXOHENABLE) ............ 60
RECEIVE UTOPIA INTERFACE ...................................................................................... 61
RECEIVE UTOPIA INTERFACE ............................................................................................................... 61
FIGURE 23. TIMING DIAGRAM FOR THE RECEIVE UTOPIA INTERFACE BLOCK .................................................................................. 61
TABLE 14: TIMING INFORMATION FOR THE RECEIVE UTOPIA INTERFACE BLOCK ............................................................................. 61
REGISTER MAP OF THE XRT79L71 ............................................................................. 63
COMMONCONTROL REGISTERS OF THE XRT79L71 ...................................................................................... 63
CLEAR-CHANNEL FRAMER BLOCK REGISTERS ................................................................................. 64
LIU/JITTER ATTENUATOR CONTROL REGISTERS .............................................................................. 68
RECEIVE ATM CELL PROCESSOR/PPP PROCESSOR BLOCK CONTROL REGISTERS................... 69
OPERATION BLOCK INTERRUPT REGISTER BIT FORMATS .................................... 77
OPERATION CONTROL REGISTER - BYTE 3 (ADDRESS = 0X0100) ................................................................. 77
OPERATION CONTROL REGISTER - BYTE 2 (ADDRESS = 0X0101) ................................................................. 77
OPERATION CONTROL - LOOP-BACK CONTROL REGISTER (ADDRESS = 0X0102) ........................................... 78
OPERATION CONTROL REGISTER - BYTE 0 (ADDRESS = 0X0103) ................................................................. 79
DEVICE ID REGISTER (ADDRESS = 0X0104) ................................................................................................. 79
REVISION ID REGISTER (ADDRESS = 0X0105).............................................................................................. 80
OPERATION INTERRUPT STATUS REGISTER - BYTE 1 (ADDRESS = 0X0112) .................................................. 80
OPERATION INTERRUPT STATUS REGISTER - BYTE 0 (ADDRESS = 0X0113) .................................................. 81
OPERATION INTERRUPT ENABLE REGISTER - BYTE 1 (ADDRESS = 0X0116) .................................................. 82
OPERATION INTERRUPT ENABLE REGISTER - BYTE 0 (ADDRESS = 0X0117) .................................................. 83
CHANNEL INTERRUPT INDICATION REGISTERS ....................................................... 84
CHANNEL INTERRUPT INDICATOR - RECEIVE CELL PROCESSOR/PPP PROCESSOR BLOCK (ADDRESS = 0X0119)84
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