XRT79L71 Datasheet, PDF (39/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L71
REV. P1.0.3
PIN #
A8
B6
D4
NAME
RxOHFrame/
RxHDLCDat_4
RxFrame
RxCellRxed
TYPE
O
0
O
DESCRIPTION
Receive Overhead Data Interface - Framing Pulse indicator/Receive HDLC
Controller Data Bus - Bit 4 output:
The function of this output pins depends upon whether the XRT79L71 has been
configured to operate in the Clear-Channel Framer Mode or in the High-Speed
HDLC Controller Mode.
Clear-Channel Framer Mode - RxOHFrame:
This output pin pulses "High" whenever the Receive Overhead Data Output
Interface block outputs the first overhead bit of a new DS3 or E3 frame.
High-Speed HDLC Controller Mode - RxHDLCDat_4:
This output pin along with RxHDLCDat_[3:0] and RxHDLCDat_[7:5] functions
as the Receive HDLC Controller byte wide output data bus. The Receive HDLC
Controller will output the contents of all HDLC frames via this output data bus,
upon the rising edge of the RxHDLCClk output signal. Hence, the user's local
terminal equipment should be designed/configured to sample this data upon the
falling edge of the RxHDLCClk output clock signal.
Receive Boundary of DS3 or E3 Frame Output indicator:
The function of this output pin depends upon whether or not the XRT79L71 is
operating in the Clear-Channel Framer/Nibble-Parallel Mode.
Clear-Channel Framer/Nibble-Parallel Mode:
The Receive Section of the XRT79L71 will pulse this output pin "High" for one
nibble period, when the Receive Payload Data Output interface block is driving
the very first nibble of a given DS3 or E3 frame, on the RxNib[3:0] output pins.
Clear-Channel Framer/Serial Mode:
The Receive Section of the XRT79L71 will pulse this output pin "High" for one
bit period, when the Receive Payload Data Output interface block is driving the
very first bit of a given DS3 or E3 frame, on the RxSer output pin.
All Other Modes:
The Receive Section of the XRT79L71 will pulse this output pin "High" when the
Receive DS3/E3 Framer block is processing the first bit within a new DS3 or E3
frame.
Receive Cell Processor - Cell Received Indicator:
This output pin pulses "High" each time the Receive Cell Processor receives a
new cell from the Receive PLCP Processor or the Receive DS3/E3 Framer
block.
NOTE: This output pin is only active if the XRT79L71 has been configured to
operate in the ATM UNI Mode.
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