XRT79L71 Datasheet, PDF (359/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L71
REV. P1.0.3
BIT NUMBER
NAME
0
Regenerate HEC Byte
Enable
TYPE
DESCRIPTION
R/W Regenerate HEC Byte Enable:
This READ/WRITE bit-field permits the user to configure the Trans-
mit ATM Cell Processor block to automatically re-compute and insert
a new HEC byte into each ATM cell (that it receives from the Trans-
mit UTOPIA Interface block) that contains an uncorrectable HEC
byte.
0 - Does not configure the Transmit ATM Cell Processor block to
compute and insert a new HEC byte into ATM cells that contains an
"uncorrectable" HEC Byte error.
1 - Configures the Transmit ATM Cell Processor block to compute
and insert a new HEC byte into ATM cells that contains an "uncor-
rectable" HEC Byte error.
TRANSMIT ATM CELL PROCESSOR BLOCK - TRANSMIT ATM CONTROL - BYTE 0 (ADDRESS =
0X1F03)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
HEC Byte
Invert
HEC Byte
Transmit
Check Enable UTOPIA
Parity Check
Enable
Transmit
UTOPIA
Parity Error -
Discard
Transmit
UTOPIA -
ODD Parity
Reserved
Scrambler
Enable
R/W
R/W
R/W
R/W
R/W
R/O
R/O
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7
HEC Byte Invert
6
HEC Byte Check Enable
TYPE
DESCRIPTION
R/W HEC Byte Invert:
This READ/WRITE bit-field permits the user to configure the Trans-
mit ATM Cell Processor block to invert each bit within the newly com-
puted HEC byte of each outbound ATM cell.
0 - Configures the Transmit ATM Cell Processor block to NOT invert
the HEC byte values that it inserts into the fifth octet position within
each outbound ATM cell.
1 - Configures the Transmit ATM Cell Processor block to invert each
bit-field within the newly computed HEC, prior to inserting it into the
fifth octet position, within each outbound ATM cell.
R/W HEC Byte Check Enable:
This READ/WRITE bit-field permits the user to configure the Trans-
mit ATM Cell Processor block to perform HEC byte checking of all
ATM cells that it receives via the Transmit UTOPIA Interface block.
0 - Configures the Transmit ATM Cell Processor block to NOT per-
form HEC byte checking on all ATM cells that it receives via the
Transmit UTOPIA Interface block.
1 - Configures the Transmit ATM Cell Processor block to perform
HEC byte checking on all ATM cells that it receives via the Transmit
UTOPIA Interface block.
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