XRT79L71 Datasheet, PDF (62/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

XRT79L71
REV. P1.0.3
PRELIMINARY
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1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
TABLE 10: TIMING INFORMATION FOR THE TRANSMIT UTOPIA INTERFACE BLOCK
SYMBOL
PARAMETER
MIN.
TYP
MAX.
UNITS
t11 TxUClav signal valid (not Hi-Z) from first TxUClk rising edge of
3.6
valid and correct TxUAddr[4:0]
9.7
ns
t12 TxUClav signal Hi-Z from first TxUClk rising edge of different
3.6
TxUAddr[4:0]
9.7
ns
TRANSMIT PAYLOAD DATA INPUT INTERFACE
TRANSMIT PAYLOAD DATA INPUT INTERFACE - TIMING REQUIREMENTS
TABLE 11: TIMING INFORMATION FO RTHE TRNASMIT PAYLOAD DATA INPUT INTERFACE BLOCK
Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified
SYMBOL
PARAMETER
MIN. TYP. MAX. UNITS
Transmit Payload Data Input Interface - Loop-Timed/Serial Mode (See Figure 13)
t₁
Payload data (TxSer) set-up time to rising edge of
12
ns
RxOutClk
CONDITIONS
t₂
Payload data (TxSer) hold time, from rising edge of
0
ns
RxOutClk
t₃
RxOutClk to TxFrame output delay
5
ns
t₄
RxOutClk to TxOHInd output delay
6
ns
Transmit Payload Data Input Interface - Local Timed/Serial Mode (See Figure 14)
t₅
Payload data (TxSer) set-up time to rising edge of
4
ns
TxInClk
t₆
Payload data (TxSer) hold time, from rising edge of
0
ns
TxInClk
t₇
TxFrameRef set-up time to rising edge of TxInClk
2
ns
Framer IC is
Frame Slave
t₈
TxFrameRef hold-time, from rising edge of TxInClk
0
ns
Frame IC is
Frame Slave
t₉
TxInClk to TxOHInd output delay
15
ns
t₁₀ TxInClk to TxFrame output delay
13
ns
Transmit Payload Data Input Interface - Looped-Timed/Nibble Mode (See Figure 15)
t₁₁ TxNib set-up time to third rising edge of RxOutClk
30
ns
t₁₂ Payload Nibble hold time, from latching edge of
30
ns
RxOutClk
t₁₃ TxNibClk to TxNibFrame output delay
25
ns DS3 Applications
31
ns E3 Applications
t_13A Max Delay of Rising Edge of TxNibClk to Data Valid
20
on TxNib[3:0]
27
Transmit Payload Data Input Interface - Local-Timed/Nibble Mode (See Figure 16
ns DS3 Applications
ns E3 Applications
50