XRT79L71 Datasheet, PDF (42/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

XRT79L71
REV. P1.0.3
PIN #
C6
NAME
RxPFrame/
RxOHInd
C3
RxGFC/
RxIdle
PRELIMINARY
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1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
TYPE
O
O
DESCRIPTION
Receive PLCP Frame Indicator/Receive Overhead Indicator Output:
The function of this output pin depends upon whether the XRT79L71 has been
configured to operate in the ATM/PLCP, the Clear-Channel Framer/Serial or the
Clear-Channel Framer/Nibble-Parallel Modes.
ATM/PLCP Mode - RxPFrame:
This output pin pulses "High" when the Receive PLCP Processor is receiving
the last bit of a PLCP frame.
NOTE: This output pin is inactive if the XRT79L71 is configured to operate in the
Direct-Mapped ATM Mode.
Clear-Channel Framer/Serial Mode - RxOHInd:
This output pin pulses "High" for one bit-period whenever an overhead bit is
being output via the RxSer output pin, by the Receive Payload Data Output
Interface block.
NOTE:
If the user configures the XRT79L71 to operate in the Gapped-Clock
Mode, then this output pin will provide a demand clock to the local
terminal equipment. In the Gapped-Clock Mode, this output pin will only
provide a clock pulse, whenever a payload bit is being output via the
RxSer output pin. This output pin will NOT generate a clock pulse,
whenever an overhead is being output via the RxSer output pin.
Clear-Channel Framer/Nibble-Parallel - RxOHInd:
This output pin pulse "High" for one nibble-period whenever an overhead nibble
is being output via the RxNib[3:0] output pins by the Receive Payload Data Out-
put Interface block.
NOTE: The purpose of this output pin is to alert the local terminal equipment
that an overhead bit (or nibble) is being output via the RxSer or
RxNib[3:0] output pins and that this data should be ignored.
Receive GFC Nibble Field - Output Pin/Receive Idle Sequence Indicator:
The function of this output pin depends upon whether the XRT79L71 is operat-
ing in the ATM Mode or in the High-Speed HDLC Controller Mode.
ATM Mode - RxGFC:
This pin, along with the RxGFCClk and the RxGFCMSB pins form the Receive
GFC Nibble-Field serial output port. This pin will serially output the contents of
the GFC Nibble field of each cell that is processed via the Receive Cell Proces-
sor. This data is serially clocked out of this pin on the rising edge of the RxGFC-
Clk signal. The MSB of each GFC value is designated by a pulse at the
RxGFCMSB output pin.
High-Speed HDLC Controller Mode - RxIdle:
The combination of the RxIdle and ValidFCS output signals are used to convey
information about data that is being output via the Receive HDLC Controller out-
put Data bus (RxHDLCDat_[7:0]).
If RxIdle = "High":
The Receive HDLC Controller block will drive this output pin "High" anytime the
flag sequence octet (0x7E) is present on the RxHDLCDat[7:0] output data bus.
If RxIdle and ValidFCS are both "High":
The Receive HDLC Controller block has received a complete HDLC frame, and
has determined that the FCS value within this HDLC frame are valid.
If RxIdle is "High" and ValidFCS is "Low":
The Receive HDLC Controller block has received a complete HDLC frame, and
has determined that the FCS value within this HDLC frame is invalid.
If RxIdle is "High" and ValidFCS is "Low":
The Receive HDLC Controller block has received an ABORT sequence.
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