EP7211 Datasheet, PDF (96/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.3.2 INTMR1 Interrupt Mask Register 1
ADDRESS: 0x8000.0280
7
EINT3
6
EINT2
5
EINT1
4
CSINT
3
MCINT
2
WEINT
1
BLINT
0
EXTFIQ
15
SSEOTI
14
UMSINT
13
URXINT
12
UTXINT
11
TINT
10
RTCMI
9
TC2OI
8
TC1OI
This interrupt mask register is a 32-bit read/write register, which is used to selectively enable any of
the first 16 interrupt sources within the EP7211. The four shaded interrupts all generate a fast
interrupt request to the ARM720T processor (FIQ), this will cause a jump to processor virtual
address 0000.0001C. All other interrupts will generate a standard interrupt request (IRQ), this will
cause a jump to processor virtual address 0000.00018. Setting the appropriate bit in this register
enables the corresponding interrupt. All bits are cleared by a system reset. Please refer to the INTSR1
register for individual bit details
5.3.3 INTSR2 Interrupt Status Register 2
ADDRESS: 0x8000.1240
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
SS2TX
1
SS2RX
0
KBDINT
15
Reserved
14
Reserved
13
URXINT2
12
UTXINT2
11
Reserved
10
Reserved
9
Reserved
8
Reserved
This register is an extension of INTSR1, containing status bits for backward compatibility with CL-
PS7111. The interrupt status register also reflects the current state of the new interrupt sources within
the EP7211. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given
below.
Bit
0
1
Description
KBDINT: Keyboard interrupt. This interrupt is generated whenever a key is pressed, from the logical OR of
the first 6 or all 8 of the Port A inputs (depending on the state of the KBD6 bit in the SYSCON2 register.
The interrupt request is latched, and can be de-asserted by writing to the KBDEOI location.
NOTE: KBDINT is not deglitched.
SS2RX: Synchronous serial interface 2 receive FIFO half or greater full interrupt. This is generated when
RX FIFO contains 8 or more half-words. This interrupt is cleared only when the RX FIFO is emptied or one
SSI2 clock after RX is disabled.
96
Register Descriptions
DS352PP3
JUL 2001