EP7211 Datasheet, PDF (83/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Address
0x8000.2000
0x8000.2040
0x8000.2080
0x8000.20C0
0x8000.2100
0x8000.2200
0x8000.2240
0x8000.2280
0x8000.22C0
0x8000.2300–
0xBFFF.FFFF
Table 5-2. Internal I/O Memory Locations (EP7211 Only)
Name
MCCR
MCDR0
MCDR1
MCDR2
MCSR
SYSCON3
INTSR3
INTMR3
Ledflsh
Reserved
Default
—
0
0
0
—
0
0
0
0
RD/WR
RW
RW
RW
RW
RD
RW
RD
RW
RW
Size
32
32
32
32
32
8
8
8
7
Comments
MCP Control Register
MCP Data Register0
MCP Data Register1
MCP Data Register2
MCP Status Register
System control register 3
Interrupt status register 3
Interrupt mask register 3
LED Flash control Register
This area contains test registers used during
manufacturing test. Writes to this area should
never be attempted during normal operation as
this may cause unexpected behavior. Reads will
be undefined.
Address
0x8000.0003
0x8000.0002
0x8000.0001
0x8000.0000
0x8000.0043
0x8000.0042
0x8000.0041
0x8000.0040
Table 5-3. Port Byte Addresses in Big Endian Mode
Name
PADR
PBDR
—
PDDR
PADDR
PBDDR
—
PDDDR
Default
0
0
0
0
0
0
RD/WR
RW
RW
—
RW
RW
RW
—
RW
Size
8
8
8
8
8
8
8
8
Comments
Port A data register
Port B data register
Reserved
Port D data register
Port A data direction register
Port B data direction register
Reserved
Port D data direction register
All internal registers in the EP7211 are reset (cleared to zero) by a system reset (i.e., NPOR,
NRESET, or NPWRFL signals becoming active), except for the DRAM refresh period register
(DRFPR), and the realtime clock data register (RTCDR) and match register (RTCMR), which are
only reset by NPOR becoming active. This ensures that the DRAM contents and system time
preserved through a user reset or power fail condition.
DS352PP3
JUL 2001
83
Register Descriptions