EP7211 Datasheet, PDF (121/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
on the opposite data direction (towards the EP7211 SIBDIN), the UCB1100 automatically forces
bits 0 through 3 to zero before transmitting the value to the MCP. Normally, the applications program
will justify the received audio data inside the nominal data word (16-bit) accordingly, before using it.
The following figure shows MCDR0. Note that the transmit and receive audio FIFOs are cleared
when the device is reset, or by writing a zero to MCE (MCP disabled). Also, note that writes to
reserved bits are ignored and reads return zeros.
Address: 0x 8000 2008
MCP Data Register 0: MCDR0
Read/Write
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bottom of Audio Receive FIFO
0000
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Read Access
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Top of Audio Transmit FIFO
0000
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Write Access
Figure 5-1. MCP Data Register 0: MCDR0
DS352PP3
JUL 2001
121
Register Descriptions