EP7211 Datasheet, PDF (64/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
The pixel bit rate, and hence the LCD refresh rate, can be programmed from 18.432 MHz to 576 kHz
when operating in 18.432–73.728 MHz mode, or 13 MHz to 203 kHz when operating from a 13 MHz
clock. The LCD controller is programmed by writing to the LCD control register (LCDCON). The
LCDCON register should not be reprogrammed while the LCD controller is enabled.
The LCD controller also contains two 32-bit palette registers, which allow any 4-, 2-, or 1-bit pixel
value to be mapped to any of the 16 grey scale values available. The required DMA bandwidth to
support a ½ VGA panel displaying 4-bits-per-pixel data at an 80 Hz refresh rate is approximately 6.2
Mbytes/sec. Assuming the frame buffer is stored in a 32-bit wide, 50 ns EDO DRAM bank, the
maximum theoretical bandwidth available is 86 Mbytes/sec at 36.864 MHz, or 29.7 Mbytes/sec at
13 MHz. If a 16-bit wide, 50 ns EDO DRAM bank is used, this drops to 30 Mbytes/sec at 36.864
MHz; still leaving sufficient bandwidth for other memory activity.
The LCD controller uses a nine stage 32-bit wide FIFO to buffer display data. The LCD controller
requests new data when there are five words remaining in the FIFO. This means that for a ½ VGA
display at 4-bits-per-pixel and 80 Hz refresh rate, the maximum allowable DMA latency is approx.
3.2 µs (640 x 240 x 4bpp x 80 Hz/8 bits/byte x 5 words (=20 bytes) = 3.2 µs). The worst-case latency
is the total number of cycles from when the DMA request appears to when the first DMA data word
actually becomes available at the FIFO. DMA has the highest priority, so it will always happen next
in the system. The worst case latency will occur when the CPU is doing a STM (store multiple)
instruction of all 16 registers to DRAM, which it has to complete before the DMA can get access to
the bus. The maximum number of cycles required is 36 from the point at which the DMA request
occurs to the point at which the STM is complete (see DRAM timing diagrams), then another 6
cycles before the data actually arrives at the FIFO from the first DMA read. This creates a total of 42
cycles. Assuming the frame buffer is located in 32-bit wide, 70 ns FPM or EDO DRAM memory,
the worst case latency is almost exactly 3.2 µs, with 13 MHz page mode cycles. With each cycle
consuming ~77 ns (i.e., 1/13 MHz), the value of 3.2 µs comes from 42 cycles x 77 ns/cycle = ~3.23
µs. If 16-bit wide, 70ns FPM or EDO DRAM is being used, then the worst case latency will double.
In this case, the maximum permissible display size will be halved, to approx. 320 x 240 pixels,
assuming the same pixel depth and refresh rate has to be maintained. If the frame buffer is to be
stored in static memory, then further calculations must be performed. If 18 MHz mode is selected,
and 32-bit wide, 70 ns FPM or EDO DRAM is being used, then the worst case latency will be 2.26
µs (i.e., 42 cycles x 54 ns/cycle). If 36 MHz mode is selected, and 32-bit wide, 50 ns EDO DRAM
is being used, then the worst case latency drops down to 1.49 µs. This calculation is a little more
complex for 36 MHz mode of operation. The total number of cycles = (12 x 4) + 7 = 55. Thus, 55 x
27 ns = ~1.49 µs.
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Functional Description
DS352PP3
JUL 2001