EP7211 Datasheet, PDF (90/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.2.3 SYSCON3 System Control Register 3
ADDRESS: 0x8000.2200
15
Reserved
14
Reserved
13
Reserved
12
Reserved
11
Reserved
10
Reserved
9
Reserved
8
FASTWAKE
7
VERSN[2]R
eserved
6
VERSN[1]
Reserved
5
VERSN[0]
Reserved
4
ADCCKNSEN
3
MCPSEL
2
CLKCTL1
1
CLKCTL0
0
ADCCON
This register is an extension of SYSCON1 and SYSCON2, containing additional control for the
EP7211. The bits of this third system control register are defined below.
Bit
8
5:7
4
3
0
1:2
Description
FASTWAKE: When set, the device will wake from the Standby State within one to two cycles of a 4 kHz
clock. This bit is cleared at power up, and thus the device first starts using the default one to two cycles of
the 8 Hz clock.
VERSN[2:0]: Additional read-only version bits — will read ‘000’.
ADCCKNSEN: When set, configuration data is transmitted on ADCOUT at the rising edge of the ADC-
CLK, and data is read back on the falling edge on the ADCIN pin. When clear (default), the opposite
edges are used.
MCPSEL: When set selects the MCP. This defaults to either the SSI or codec (i.e., MCPSEL bit is low).
ADCCON: Determines whether the ADC Configuration Extension field SYNCIO(31:16) is to be used for
ADC configuration data. When this bit = 0 (default state) the ADC Configuration Byte SYNCIO(7:0) only is
used for compatibility with the CL-PS7111. When this bit = 1, the ADC Configuration Extension field in the
SYNCIO register is used for ADC Configuration data and the value in the ADC Configuration Byte (SYN-
CIO(6:0)) selects the length of the data (8-bit to 16-bit).
CLKCTL(1:0): Determines the frequency of operation of the processor and Wait State scaling. The table
below lists the available options.
CLKCTL(1:0)
Value
00
01
10
11
Processor
Frequency
18.432 MHz
36.864 MHz
49.152 MHz
73.728 MHz
ASB and APB
Frequency
18.432 MHz
36.864 MHz
36.864 MHz
36.864 MHz
Wait State
Scaling
1
2
2
2
NOTE: To determine the number of wait states programmed refer to Table 5-4. Values of the Wait State
Field at 13 and 18MHz and Table 5-5. Values of the Wait State Field at 36 MHz. When operating at 13
MHz, the CLKCTL[1:0] bits should not be changed from the default value of ‘00’. Under no circumstances
should the CLKCTL bits be changed using a buffered write.
90
Register Descriptions
DS352PP3
JUL 2001