EP7211 Datasheet, PDF (150/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
7. TEST MODES
The EP7211 supports a number of hardware activated test modes, these are activated by the pin
combinations shown in the Table 7-1. EP7211 Hardware Test Modes. All latched signals will only
alter test modes while NPOR is low, their state is latched on the rising edge of NPOR. This allows
these signals to be used normally during various test modes.
Table 7-1. EP7211 Hardware Test Modes
Test Mode
Normal operation
(32-bit boot)
Normal operation
(8-bit boot)
Normal operation
(16-bit boot)
Alternative test ROM boot
Oscillator / PLL bypass
Oscillator / PLL test mode
ICE Mode
System test (all HiZ)
Latched
NMEDCHG
1
1
1
0
X
X
X
X
Latched
PE0
0
1
0
X
X
X
X
X
Latched
PE1
0
Latched
NURESET
X
NTEST0
1
0
X
1
1
X
1
X
X
1
X
X
1
X
0
0
X
1
0
X
0
0
NTEST1
1
1
1
1
0
1
0
0
Within each test mode, a selection of pins is used as multiplexed outputs or inputs to provide/monitor
the test signals unique to that mode.
7.1 Oscillator and PLL Bypass Mode
This mode is selected by NTEST0 = 1, NTEST1 = 0.
In this mode all the internal oscillators and PLL are disabled and the appropriate crystal oscillator
pins become the direct external oscillator inputs bypassing the oscillator and PLL. MOSCIN must be
driven by a 36.864 MHz clock source and RTCIN by a 32.768 kHz source.
7.2 Oscillator and PLL Test Mode
This mode is selected by NTEST0 = 0, NTEST1 = 1, Latched NURESET = 0
This test mode will enable the main oscillator and it will output various buffered clock and test
signals derived from the main oscillator, PLL, and 32-kHz oscillator. All internal logic in the EP7211
will be static and isolated from the oscillators, with the exception of the 6-bit ripple counter used to
generate 576 kHz and the real time clock divide chain. Port A is used to drive the inputs of the PLL
directly, and the various clock and PLL outputs are monitored on the COL pins. Table 7-2.
150
Test Modes
DS352PP3
JUL 2001