EP7211 Datasheet, PDF (127/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
FIFO such that four or more locations are filled within the telecom transmit FIFO, the TTS flag (and
the service request and/or interrupt) is automatically cleared.
5.16.3.4 Telecom Receive FIFO Service Request Flag (TRS) (read-only, maskable
interrupt)
The telecom receive FIFO service request flag (TRS) is a read-only bit which is set when the telecom
receive FIFO is nearly filled and requires service to prevent an overrun. TRS is set any time the
telecom receive FIFO has six or more entries of valid data (half full or more), and cleared when it
has five or fewer (less than half full) entries of data. When the TRS bit is set, an interrupt request is
made unless the telecom receive FIFO interrupt request mask (TRM) bit is cleared. After six or more
entries are removed from the receive FIFO, the TRS flag (and the service request and/or interrupt) is
automatically cleared.
5.16.3.5 Audio Transmit FIFO Underrun Status (ATU) (read/write, non-maskable interrupt)
The audio transmit FIFO underrun status bit (ATU) is set when the audio transmit logic attempts to
fetch data from the FIFO after it has been completely emptied. When an underrun occurs, the audio
transmit logic continuously transmits the last valid audio value which was transmitted before the
underrun occurred. Once data is placed in the FIFO and it is transferred down to the bottom, the audio
transmit logic uses the new value within the FIFO for transmission. When the ATU bit is set, an
interrupt request is made.
5.16.3.6 Audio Receive FIFO Overrun Status (ARO) (read/write, non-maskable interrupt)
The audio receive FIFO overrun status bit (ARO) is set when the audio receive logic attempts to
place data into the audio receive FIFO after it has been completely filled. Each time a new piece of
data is received, the set signal to the ARO status bit is asserted, and the newly received data is
discarded. This process is repeated for each new sample received until at least one empty FIFO entry
exists. When the ARO bit is set, an interrupt request is made.
5.16.3.7 Telecom Transmit FIFO Underrun Status (TTU) (read/write, non-maskable
interrupt)
The telecom transmit FIFO underrun status bit (TTU) is set when the telecom transmit logic attempts
to fetch data from the FIFO after it has been completely emptied. When an underrun occurs, the
telecom transmit logic continuously transmits the last valid telecom value which was transmitted
before the underrun occurred. Once data is placed in the FIFO and it is transferred down to the
bottom, the telecom transmit logic uses the new value within the FIFO for transmission. When the
TTU bit is set, an interrupt request is made.
5.16.3.8 Telecom Receive FIFO Overrun Status (TRO) (read/write, non-maskable
interrupt)
The telecom receive FIFO overrun status bit (TRO) is set when the telecom receive logic places data
into the telecom receive FIFO after it has been completely filled. Each time a new piece of data is
received, the set signal to the TRO status bit is asserted, and the newly received sample is discarded.
DS352PP3
JUL 2001
127
Register Descriptions