EP7211 Datasheet, PDF (74/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
CLKEN timing — coming out of STDBY
EXPCLK
(int) RUN
T42
CLKEN
Intr./
WAKEUP
NOTE: T42 = 0.125 s to 0.25
s
Figure 3-12. CLKEN Timing Leaving the Standby State
3.18 Dynamic Clock Switching When in the PLL Clocking Mode
The clock frequency used for the CPU and the buses is controlled by programming the
CLKCTL[1:0] bits in the SYSCON3 register. When this occurs, the state controller switches from
the current to the new clock frequency as soon as possible without causing a glitch on the clock
signals. The glitch-free clock switching logic waits until the clock that is currently in use and the
newly programmed clock source are both low, and then switches from the previous clock to the new
clock without a glitch on the clocks.
3.19 Endianness
The EP7211 uses a Little Endian configuration for internal registers. However, it is possible to
connect the device to a Big Endian external memory system. The bigend bit in the ARM720T control
register sets whether the EP7211 treats words in memory as being stored in Big Endian or Little
Endian format. Memory is viewed as a linear collection of bytes numbered upwards from zero. Bytes
0 to 3 hold the first stored word, bytes 4 to 7 the second, and so on. In the Little Endian scheme, the
lowest numbered byte in a word is considered to be the least significant byte of the word and the
highest numbered byte is the most significant. Byte 0 of the memory system should be connected to
data lines 7 through 0 (D[7:0]) in this scheme. In the Big Endian scheme the most significant byte of
a word is stored at the lowest numbered byte, and the least significant byte is stored at the highest
numbered byte. Therefore, Byte 0 of the memory system should be connected to data lines 31
through 24 (D[31:24]). Load and store are the only instructions affected by the Endianness.
The following tables demonstrate the behavior of the EP7211 in Big and Little Endian mode,
including the effect of performing non-aligned word accesses. The register definition section of this
74
Functional Description
DS352PP3
JUL 2001