EP7211 Datasheet, PDF (118/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
controller. When TRM = 1, the interrupt is enabled and whenever TRS is set (one) an interrupt
request is made to the interrupt controller. Note that programming TRM = 0 does not affect the
current state of TRS or the telecom receive FIFO logic’s ability to set and clear TRS, it only blocks
the generation of the interrupt request.
5.16.1.8 Audio Transmit FIFO Interrupt Mask (ATM)
The audio transmit FIFO interrupt mask (ATM) bit is used to mask or enable the audio transmit FIFO
service request interrupt. When ATM = 0, the interrupt is masked and the state of the audio transmit
FIFO service request (ATS) bit within the MCP status register is ignored by the interrupt controller.
When ATM = 1, the interrupt is enabled and whenever ATS is set (one) an interrupt request is made
to the interrupt controller. Note that programming ATM = 0 does not affect the current state of ATS
or the audio transmit FIFO logic’s ability to set and clear ATS; it only blocks the generation of the
interrupt request.
5.16.1.9 Audio Receive FIFO Interrupt Mask (ARM)
The audio receive FIFO interrupt mask (ARM) bit is used to mask or enable the audio receive FIFO
service request interrupt. When ARM = 0, the interrupt is masked and the state of the audio receive
FIFO service request (ARS) bit within the MCP status register is ignored by the interrupt controller.
When ARM = 1, the interrupt is enabled and whenever ARS is set (one) an interrupt request is made
to the interrupt controller. Note that programming ARM = 0 does not affect the current state of ARS
or the audio receive FIFO logic’s ability to set and clear ARS; it only blocks the generation of the
interrupt request.
5.16.1.10 Loop Back Mode (LBM)
The loop back mode (LBM) bit is used to enable and disable the ability of the MCP’s transmit and
receive logic to communicate. When LBM = 0, the MCP operates normally. The transmit and receive
data paths are independent and communicate via their respective pins. When LBM = 1, the output of
the serial shifter (MSB) is directly connected to the input of the serial shifter (LSB) internally and
control of the SIBDOUT, SIBDIN, SIBCLK, and SIBSYNC pins are given to the peripheral pin
control (PPC) unit.
The following figure shows the bit locations corresponding to the ten different control bit fields
within the MCP control register. Note that the MCE bit is the only control bit which is reset to a
known state to ensure the MCP is disabled following a reset of the device. The reset state of all other
control bits is unknown and must be initialized before enabling the MCP. Writes to reserved bits are
ignored and reads return zeros.
118
Register Descriptions
DS352PP3
JUL 2001