EP7211 Datasheet, PDF (61/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Data on the link is sent MSB first and coincides with an appropriate frame sync pulse, of one clock
in duration, located one clock prior to the first data bit sent (i.e., MSB). It is not possible to send data
LSB first.
When operating in master mode, the clock frequency is selected to be the same as the ADC
interface’s (master mode only SSI1) — that is, the frequencies are selected by the same bits 16 and
17 of the SYSCON1 register (i.e., the ADCKSEL bits). Thus, the maximum frequency in master
mode is 128 kbytes/s. The interface will support continuous transmission at this rate assuming that
the OS can respond to the interrupts within 1 ms to prevent over/underruns.
NOTE: To allow synchronization to the incoming slave clock, the interface enable bits will not take effect until
one SSICLK cycle after they are written and the value read back from SYSCON2. The enable bits
reflect the real status of the enables internally. Hence, there will be a delay before the new value pro-
grammed to the enable bits can be read back.
The timing diagram for this interface can be found in the AC Characteristics section of this
document.
3.8.4.1 Read Back of Residual Data
All writes to the transmit FIFO must be in half-words (i.e., in units of two bytes at a time). On the
receive side, it is possible that an odd number of bytes will be received. Bytes are always loaded into
the receive FIFO in pairs, so in the case of a single residual byte remaining at the end of a
transmission, it will be necessary for the software to read the byte separately. This is done by reading
the status of two bits in the SYSFLG2 register to determine the validity of the residual data. These
two bits (RESVAL, RESFRM) are both set high when a residual is valid; RESVAL is cleared on
either a new transmission or on reading of the residual bit by software. RESFRM is cleared only on
a new transmission. By popping the residual byte into the RX FIFO and then reading the status of
these bits it is possible to determine if a residual bit has been correctly read.
Figure 3-8. Residual Byte Reading illustrates this procedure. The sequence is as follows: read the
RESVAL bit, if this is a 0, no action needs to be taken. If this is a 1, then pop the residual byte into
the FIFO by writing to the SS2POP location. Then read back the two status bits RESVAL and
RESFRM. If these bits read back 01, then the residual byte popped into the FIFO is valid and can be
read back from the SS2DR register. If the bits are not 01, then there has been another transmission
received since the residual read procedure has been started. The data item that has been popped to
the top of the FIFO will be invalid and should be ignored. In this case, the correct byte will have been
stored in the most significant byte of the next half-word to be clocked into the FIFO.
DS352PP3
JUL 2001
61
Functional Description