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EP7211 Datasheet, PDF (79/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
4. MEMORY MAP
The lower 2 GByte of the address space is allocated to ROM/SRAM/Flash and expansion space. The
0.5 Gbyte of address space from 0xC0000000 to 0xDFFFFFFF is allocated to DRAM. The
remaining 1.5 Gbyte, less 8K for internal registers, is not accessible in the EP7211. The MMU in the
EP7211 should be programmed to generate an abort exception for access to this area.
Internal peripherals are addressed through a set of internal memory locations from hex address
8000.0000 to 8000.3FFF. These are known as the internal registers in the EP7211.
Figure 4-1 shows how the 4-Gbyte address range of the ARM720T processor (as configured within
this chip) is mapped in the EP7211. The memory map shown assumes that two CL-PS6700 PC Card
controllers are connected. If this functionality is not required, then the NCS4 and NCS5 memory is
available as general ROM/SRAM/Flash/Expansion space. The Boot ROM is not fully decoded (i.e.,
the Boot code will repeat within the 256-Mbyte space from 0x70000000 to 0x80000000). The
SRAM is fully decoded up to a maximum size of 128 kbytes. Access to any location above this range
will be wrapped to within the range.
Table 4-1. EP7211 Memory Map
Address
0xF000.0000
0xE000.0000
0xD000.0000
0xC000.0000
0x8000.4000
0x8000.2000
0x8000.0000
0x7000.0000
0x6000.0000
0x5000.0000
0x4000.0000
0x3000.0000
0x2000.0000
0x1000.0000
0x0000.0000
Contents
Reserved
Reserved
DRAM Bank 1
DRAM Bank 0
Unused
Internal registers (new)
Internal registers (old)
Boot ROM (NCS7)
SRAM (NCS6)
PCMCIA-1 (NCS5)
PCMCIA-0 (NCS4)
Expansion (CS3)
Expansion (CS2)
ROM Bank 1 (CS1)
ROM Bank 0 (CS0)
Size
256 Mbytes
256 Mbytes
256 Mbytes
256 Mbytes
~1 Gbyte
8 kbytes
8 kbytes
128 bytes
37.5 kbytes
4 x 64 Mbytes
4 x 64 Mbytes
256 Mbytes
256 Mbytes
256 Mbytes
256 Mbytes
DS352PP3
JUL 2001
79
Memory Map