EP7211 Datasheet, PDF (55/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Note that the transmit line is pulled low any time data is not being driven onto the pin. The UCB1100
has a programming option which allows it to either tristate or drive the receive line low when data is
not driven onto SIBDIN. As shown in Figure 3-4, the MCP frames occur back-to-back. The
SIBSYNC pin is driven high during the last clock (128th) of the frame to indicate the start of a new
frame the following SIBCLK period. Values contained within the transmit FIFOs are loaded to the
shift register on the rising-edge of SIBSYNC.
3.8.2.3 Audio and Telecom Sample Rates and Data Transfer
The UCB1100 contains an audio and telecom codec with sample rates that can be individually
programmed, and are derived from the 9.216 MHz (6.5 MHz in 13 MHz mode) serial clock
(SIBCLK), which is supplied by the MCP interface. This is derived originally from the divided chip
clock.
For the UCB1100 audio codec, with an input clock as above, valid sample rates are derived by
dividing the serial clock first by a fixed value of 32 and then by a value from 9 to 127. For the
UCB1100 telecom codec, the sample rate is derived by dividing the serial clock first by a fixed value
of 32 and then by a value from 16 to 127. Nominal sample frequencies are 7.2 kHz for the telecom
codec and 22.05 kHz for the audio codec. For a SIBCLK of 9.216 MHz, the sample rate of the
telecom codec using a divisor of 40, is exactly correct while for the audio codec, using a divisor of
13, the sample rate error is less than +0.5%. For a SIBCLK of 6.5 MHz, the sample rate error of the
telecom codec using a divisor of 28, is less than +0.75%, while for the audio codec using a divisor
of 9 the sample rate error is less than +2.5%. The codec and the MCP both contain an audio and a
telecom sample rate counter. These counters are used to achieve conversion rate synchronization
between the codec and the MCP, so that data may be coherently transferred between the MCP and
the codec. For the remainder of this description all references are made to the audio codec for brevity;
however, all information also applies to the telecom portion of the codec and the MCP.
Before enabling the audio codec, the audio sample rate counters within the codec and the MCP must
be programmed with the same divisor value so that they have the same clock rate. The codec’s audio
sample rate divisor is programmed by issuing a control register write transfer and the MCP’s divisor
is programmed using the CPU by writing to the MCP’s control register. Both the MCP and the
codec’s audio counters are reloaded with the programmed modulus value any time the audio portion
of the codec is enabled. This can also be accomplished by performing a control register write transfer
or whenever the sample rate counters reach zero.
The MCP and the audio codec decrement their counters in lock-step with one another, both starting
on the occurrence of the first SIBSYNC pulse after the audio codec is enabled. Samples/conversions
are made each time the audio codec’s counter reaches zero. Figure 3-5 shows the timing of the audio
codec enable, as well as decrements of the MCP and audio codec’s sample counter.
DS352PP3
JUL 2001
55
Functional Description