EP7211 Datasheet, PDF (47/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 3-9. Physical to DRAM Address Mapping
DRAM Address
Pins
0
1
2
3
4
5
6
7
8
9
10
11
12
DRAM
Column x16
Mode
A1*
A2
A3
A4
A5
A6
A7
A8
A18
A20
A22
A24
A26
DRAM
Column x32
Mode
A2
A3
A4
A5
A6
A7
A8
A9
A19
A21
A23
A25
A27
DRAM
Row x16
Mode
A9
A10
A11
A12
A13
A14
A15
A16
A17
A19
A21
A23
A25
DRAM
Row x32
Mode
A10
A11
A12
A13
A14
A15
A16
A17
A18
A20
A22
A24
A26
7211 Pin Name
A[27]/DRA[0]
A[26]/DRA[1]
A[25]/DRA[2]
A[24]/DRA[3]
A[23]/DRA[4]
A[22]/DRA[5]
A[21]/DRA[6]
A[20]/DRA[7]
A[19]/DRA[8]
A[18]/DRA[9]
A[17]/DRA[10]
A[16]/DRA[11]
A[15]/DRA[12]
Table 3-10 and Table 3-11. DRAM Address Mapping for a 16-Bit-Wide DRAM Memory
System show the address mapping for various DRAM’s with square and non-square row and address
inputs assuming two x16 devices are connected to each RAS line with 32-bit wide DRAM operation
selected. This mapping is then repeated every 256 Mbytes for each DRAM bank. The placeholder
‘n’ below is equal to 0xC + bank number (e.g., 0xC for bank 0, 0xD for bank 1).
DS352PP3
JUL 2001
47
Functional Description