EP7211 Datasheet, PDF (69/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 3-15. Peripheral Status in Different Power Management States
Address (W/B)
DRAM Control
UARTs
LCD FIFO
LCD
ADC Interface
SSI2 Interface
MCP Interface
Codec
Timers
RTC
LED Flasher
DC-to-DC
CPU
Interrupt Control
PLL/CLKEN Signal
Operating
Idle Standby
NPOR
RESET
NRESET
RESET
On
On SELFREF
Off
SELFREF
On
On
Off
Reset
Reset
On
On
Reset
Reset
Reset
On
On
Off
Reset
Reset
On
On
Off
Reset
Reset
On
On
Off
Reset
Reset
On
On
Off
Reset
Reset
On
On
Off
Reset
Reset
On
On
Off
Reset
Reset
On
On
On
On
On
On
On
On
Reset
Reset
On
On
Off
Reset
Reset
On
Off
Off
Reset
Reset
On
On
On
Reset
Reset
On
On
Off
Off
Off
In the Standby State, all the system memory and state is maintained and the system time is kept up-
to-date. The PLL/on-chip oscillator or external oscillator is disabled and the system is static, except
for the low power watch crystal (32 kHz) oscillator and divider chain to the RTC and LED flasher.
The RUN signal is driven low when in the Standby State. This signal can be used externally in the
system to power down other system modules.
Whenever the EP7211 is in the Standby State, the external address and data buses are driven low.
The RUN signal is used internally to force these buses to be driven low. This is done to prevent
peripherals that are powered-down from draining current. Also, the internal peripheral’s signals get
set to their Reset State.
When first powered, or reset by the NPOR (Not Power On Reset) signal, the EP7211 is forced into
the Standby State. This is known as a cold reset, and is the only completely asynchronous reset to the
EP7211. When leaving the Standby State after a cold reset, external wake up is the only way for
waking up the device. When leaving the Standby State after non-cold reset conditions (i.e., the
software has forced the device into the Standby State), the transition to the Operating State can be
caused by a rising edge on the WAKEUP input signal or by an enabled interrupt. Normally, when
entering the Standby State from the Operating State, the software will leave some interrupt sources
enabled. Once the refresh enable register bit is enabled for the DRAMs, any transition to the Standby
State will force the DRAMs to the self-refresh state before stopping the PLL or external oscillator.
DS352PP3
JUL 2001
69
Functional Description