EP7211 Datasheet, PDF (89/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Bit
5
6
8
9
12
13
14
Description
PC CARD1: Enable for the interface to the CL-PS6700 device for PC Card slot 1. The main effect of this
bit is to reassign the functionality of Port B, Bit 0 to the PRDY input from the
CL-PS6700 devices, and to ensure that any access to the NCS4 address space will be according to the
CL-PS6700 interface protocol.
PC CARD2: Enable for the interface to the CL-PS6700 device for PC Card slot 2. The main effect of this
bit is to reassign the functionality of Port B, Bit 1 to the PRDY input from the
CL-PS6700 devices, and to ensure that any access to the NCS5 address space will be according to the
CL-PS6700 interface protocol.
UART2EN: Internal UART2 enable bit. Setting this bit enables the internal UART2.
SS2MAEN: Master mode enable for the synchronous serial interface 2. When low, SSI2 will be configured
for slave mode operation. When high, SSI2 will be configured for master mode operation. This bit also con-
trols the directionality of the interface pins.
OSTB: This bit (operating system timing bit) is for use only with the 13 MHz clock source mode. Normally
it will be set low, however when set high it will cause a 500 kHz clock to be generated for the timers instead
of the 541 kHz which would normally be available. The divider to generate this frequency is not clocked
when this bit is set low.
CLKENSL: CLKEN select. When low, the CLKEN signal will be output on the RUN/CLKEN pin. When
high, the RUN signal will be output on RUN/CLKEN.
BUZFREQ: The BUZFREQ bit is used to select which hardware source will be used as the source to drive
the buzzer output pin. When BUZFREQ = 0, the buzzer signal generated from the on-chip timer (TC1) is
output. When BUZFREQ = 1, a fixed frequency clock is output
(500 Hz when running from the PLL, 528 Hz in the 13 MHz external clock mode). See the BZMOD and the
BZTOG bits for more details.
DS352PP3
JUL 2001
89
Register Descriptions