EP7211 Datasheet, PDF (113/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.13.7 UMSEOI UART1 Modem Status Changed End of Interrupt
ADDRESS: 0x8000.0780
A write to this location will clear the modem status changed interrupt.
5.13.8 COEOI Codec End of Interrupt Location
ADDRESS: 0x8000.07C0
A write to this location clears the sound interrupt (CSINT).
5.13.9 KBDEOI Keyboard End of Interrupt Location
ADDRESS: 0x8000.1700
A write to this location clears the KBDINT keyboard interrupt.
5.13.10 SRXEOF End of Interrupt Location
ADDRESS: 0x8000.1600
A write to this location clears the SSI2 RX FIFO overflow status bit.
5.14 State Control Registers
5.14.1 STDBY Enter the Standby State Location
ADDRESS: 0x8000.0840
A write to this location will put the system into the Standby State by halting the main oscillator. It
will automatically switch the DRAMs into self refresh if the RFSHEN bit is set in the DRAM refresh
period register. All transitions to the Standby State are synchronized with DRAM cycles. A write to
this location while there is an active interrupt will have no effect.
NOTE: The following restrictions apply when operating with a self-refresh DRAM
1) Before entering the Standby State, the LCD Controller should be disabled. The LCD controller should be
enabled on exit from the Standby State.
2) After exiting from the Standby State, the first instruction that gets executed must be fetched from non-
DRAM.
NOTE: If the EP7211 is attempting to get into the Standby State when there is a pending interrupt request, it
will not enter into the low power mode. The instruction will get executed, but the processor will ignore
the command.
5.14.2 HALT Enter the Idle State Location
ADDRESS: 0x8000.0800
A write to this location will put the system into the Idle State by halting the clock to the processor
until an interrupt is generated. A write to this location while there is an active interrupt will have no
effect.
DS352PP3
JUL 2001
113
Register Descriptions