EP7211 Datasheet, PDF (72/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
preserving the contents through a system reset. This is the reason the DRAM refresh period register
is not cleared by a system reset.
The NSTBY and RUN signals are high when the EP7211 is in the Operating or Idle States and low
when in the Standby State. The main system clock is valid when NSTBY is high. The NSTBY signal
will disable any peripheral block that is clocked from the master clock source (i.e., everything except
for the RTC). In general, a system reset will clear all registers and NSTBY will disable all peripherals
that require a main clock. The following peripherals are always disabled by a low level on NSTBY:
two UARTs and IrDA SIR encoder, timer counters, telephony codec, and the two SSI interfaces. In
addition, when in the Standby State, the LCD controller and PWM drive are also disabled.
When operating from an external 13 MHz oscillator which has become disabled in the Standby State
by using the CLKEN signal (i.e., with CLKENSL = 0), the oscillator must be stable within 0.125 s
from the rising edge of the CLKEN signal.
3.17 Clocks
There are two clocking modes for the EP7211. Either an external clock input can be used or the on-
chip PLL. The clock source is selected by a strapping option on Port E, Pin 2 (PE[2]). If PE[2] is
high at the rising edge of NPOR (i.e., upon power-up), the external clock mode is selected. If PE[2]
is low, then the on-chip PLL mode is selected.
The architecture for the EP7211 device contains several separate sections of logic. Some of them are
the ARM720T processor, the peripherals, and the address/data bus sections. The peripherals section
has its own dedicated bus structure called the Embedded Peripheral Bus (EPB). From the
ARM720T’s point of view, the peripherals are strobed devices. Each unique peripheral device does
have its own dedicated clock source supplied to it according to its clock frequency requirements.
However, when the EP7211 is in the PLL mode, the actual frequencies will be different than when
in the external clock mode. See each peripheral device section for more details. The section below
describes the clocking for both the ARM720T and address/data bus sections.
3.17.1 On-Chip PLL
The ARM720T clock can be programmed to run at 18.432 MHz, 36.864 MHz, 49.152 MHz or
73.728 MHz. The PLL frequency is fixed at twice the highest possible CPU clock frequency
(147.456 MHz). The PLL uses an external 3.6864 MHz crystal. On power-up, if the device has been
strapped to use the on-chip PLL, then the device will start up with both the ARM720T and
address/data buses configured to run at 18.432 MHz by default. After power-up, the clock frequency
can be changed by software. If the clock frequency is changed to be 36 MHz, both the ARM720T
and the address/data buses will be clocked at 36 MHz as well. When the clock frequency is selected
higher than 36 MHz, only the ARM720T gets clocked at this higher speed. The address/data will be
fixed at 36 MHz. The clock frequency used is selected by programming the CLKCTL[1:0] bits in the
SYSCON3 register. The clock frequency selection does not effect the individual dedicated peripheral
clock sources. In other words, all the peripheral clocks are fixed, regardless of the PLL mode clock
speed selected for the ARM720T.
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Functional Description
DS352PP3
JUL 2001