EP7211 Datasheet, PDF (92/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Bit
14
15
16:21
22
23
24
25
26
27
28
30:31
Description
PFFLG: Power Fail Flag. This bit will be set if the system has been reset by the NPWRFL input pin, it is
cleared by writing to the STFCLR location.
CLDFLG: Cold start flag. This bit will be set if the EP7211 has been reset with a power on reset, it is
cleared by writing to the STFCLR location.
RTCDIV: This 6-bit field reflects the number of 64 Hz ticks that have passed since the last increment of the
RTC. It is the output of the divide by 64 chain that divides the 64 Hz tick clock down to 1 Hz for the RTC.
The MSB is the 32 Hz output, the LSB is the 1 Hz output.
URXFE1: UART1 receiver FIFO empty. The meaning of this bit depends on the state of the UFIFOEN bit in
the UART1 bit rate and line control register. If the FIFO is disabled, this bit will be set when the RX holding
register is empty. If the FIFO is enabled the URXFE bit will be set when the RX FIFO is empty.
UTXFF1: UART1 transmit FIFO full. The meaning of this bit depends on the state of the UFIFOEN bit in
the UART1 bit rate and line control register. If the FIFO is disabled, this bit will be set when the TX holding
register is full. If the FIFO is enabled the UTXFF bit will be set when the TX FIFO is full.
CRXFE: Codec RX FIFO empty bit. This will be set if the 16-byte codec RX FIFO is empty.
CTXFF: Codec TX FIFO full bit. This will be set if the 16-byte codec TX FIFO is full.
SSIBUSY: Synchronous serial interface busy bit. This bit will be set while data is being shifted in or out of
the synchronous serial interface, when clear data is valid to read.
BOOTBIT0–1: These bits indicate the default (power-on reset) bus width of the ROM interface. See the
memory configuration register for more details on the ROM interface bus width. The state of these bits
reflect the state of Port E bits 0–1 during power on reset, as shown in the table below.
PE1 (Bootbit1)
0
0
1
1
PE0 (Bootbit0)
0
1
0
1
Boot option
32-bit
8-bit
16-bit
Reserved
ID: Will always read ‘1’ for the EP7211 device.
VERID: Version ID bits. These 2 bits determine the version id for the EP7211. Will read ‘10’ for the initial
version.
92
Register Descriptions
DS352PP3
JUL 2001