EP7211 Datasheet, PDF (53/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
codec register reads. Touch-screen and ADC conversions are triggered, and the digital I/O lines are
controlled using codec register writes, while the converted data and the state of digital I/O lines is
accessed using a codec register read.
3.8.2.1 MCP Operation
Following reset, the MCP logic is disabled. To enable the MCP the applications program should first
clear the emergency underflow and overflow status bits, which are set following the reset, by writing
a 1 to these register bits (during a MCSR read access). Next, the user should program the MCP
control register with the desired mode of operation using a word write. The user may choose to either
“prime” the audio and telecom transmit FIFOs by writing up to eight 16-bit values each, or allow the
FIFO service requests to interrupt the CPU and trigger an EPB transfer to fill the FIFOs. Once the
off-chip codec is programmed and data resides within the bottom entries of the audio and/or telecom
FIFOs, transmission/reception of data begins on the transmit (SIBDOUT) and receive (SIBDIN)
pins. This is synchronously controlled by the 9.216 MHz (6.5 MHz in 13 MHz mode) serial clock
(SIBCLK) and serial frame (SIBSYNC) pins.
3.8.2.2 MCP Frame Format
Each MCP data frame is 128 bits long and is divided into two subframes: 0 and 1. Subframe 0 is used
by the MCP to communicate data to and from the UCB1100. Subframe 1 is not used by the MCP,
since it is typically used to interface to high-performance stereo codecs like Crystal’s CS4216/18.
After the MCP is enabled, SIBCLK begins to transition at a fixed rate of 9.216 MHz (6.5 MHz in
the 13 MHz mode) and the start of the first frame is signalled by driving the SIBSYNC pin high for
one SIBCLK period. The rising-edge of SIBSYNC coincides with the rising-edge of SIBCLK, one
clock cycle immediately before each frame start. The SIBSYNC pulse causes the MCP to transfer
any available audio and/or telecom data from their respective transmit FIFOs to a 64-bit serial shifter,
setting the appropriate audio/telecom valid flags as well. If the codec control register contains valid
data, the register value and address is placed within the appropriate fields within the shifter, and the
read/write bit is configured to indicate which type of register access is to be made. For any field that
does not have valid data available, the previous value transmitted is used. As long as the MCP is
enabled, data frames are continuously transferred, even if valid data may not be available for
transmission. The format of data transmitted and received in subframe 0 is shown in Figure 3-3.
Data Format of MCP Subframe 0. Note that the UCB1100 data sheet uses Big Endian notation to
specify the MCP frame bit positions; however, Little Endian notation is used here to remain
consistent with the rest of the device specification.
DS352PP3
JUL 2001
53
Functional Description