EP7211 Datasheet, PDF (111/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
The length of the data frame can be programmed by writing to the SYNCIO register. This allows
many different ADCs to be accommodated. The device is SPI/Microwire compatible (transfers are
in multiples of 8 bits). However, to be compatible with some non-SPI/Microwire devices, the data
written to the ADC device can be anything between 8 to 16 bits. This is user-definable as defined in
the ADC Configuration Extension section of the SYNCIO register.
In the default mode, the bits in SYNCIO have the following meaning:
31:15
Reserved
14
TXFRMEN
13
SMCKEN
12:8
Frame length
Whereas in extended mode, the following applies:
7:0
ADC Configuration Byte
15
Reserved
14
TXFRMEN
13
SMCKEN
12:7
Frame length
6:0
ADC Configuration
Length
31
16
ADC Configuration Extension
NOTE: The frame length in extended mode is 6 bits wide to allow up to 16 write bits, 1 null bit and 16 read
bits (= 33 cycles).
Bit
0:7 or 0:6
8:12 or 7:12
13
14
16:31
Description
ADC Configuration Byte: When the ADCCON control bit in the SYSCON3 register = 0, this is the 8-bit
configuration data to be sent to the ADC. When the ADCCON control bit in the SYSCON3 register = 1, this
field determines the length of the ADC configuration data held in the ADC Configuration Extension field
for sending to the ADC.
Frame length: The Frame Length Field is the total number of shift clocks required to complete a data
transfer.
In default mode, MAX148/9 (and for many ADCs), this is 25 = (8 for configuration byte + 1 null bit + 16 bits
result).
In extended mode, AD7811/12, this is 23 = (10 for configuration byte + 3 null + 10 bits result).
SMCKEN: Setting this bit will enable a free running sample clock at twice the programmed ADC clock fre-
quency to be output on the SMPLCK pin.
TXFRMEN: Setting this bit will cause an ADC data transfer to be initiated. The value in the ADC configura-
tion field will be shifted out to the ADC and depending on the frame length programmed, a number of bits
will be captured from the ADC. If the SYNCIO register is written to with the TXFRMEN bit low, no ADC
transfer will take place, but the Frame length and SMCKEN bits will be affected.
ADC Configuration Extension: When the ADCCON control bit in the SYSCON3 register = 0 this field is
ignored for compatibility with the CL-PS7111. When the ADCCON control bit in the SYSCON3 register = 1,
this field is the configuration data to be sent to the ADC. The ADC Configuration Extension field length is
determined by the value held in the ADC Configuration Length field (SYNCIO[6:0]).
DS352PP3
JUL 2001
111
Register Descriptions