EP7211 Datasheet, PDF (57/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
the audio codec input and output enable bits and enables the MCP’s audio sample rate counter at the
same time as the codec’s counter to ensure synchronization.
The UCB1100 has an individual data valid bit for audio and telecom A/D samples. Whenever these
bits are set in the data frame returned from the codec to the MCP, the audio and telecom data is taken
from the frame and placed in their respective receive FIFO. There are two different modes of
operation to control the setting of the audio and telecom data valid bits. The UCB1100 uses both
modes. In the first mode, a data valid bit is set any time a frame contains “reliable” data, (i.e., the
codec is enabled and at least one A/D sample has been taken). In this mode, once the data valid bit
is set, it remains set until the codec A/D input is disabled. In the second mode, the codec only sets
the data valid bit corresponding to a new A/D sample. Once, the data is transmitted to the MCP
within a receive data frame, the data valid bit is reset to zero for subsequent data frames until a new
A/D sample is triggered.
3.8.2.4 MCP FIFO Operation
The MCP contains two 8-word deep, 16-bit audio/telecom transmit FIFOs and two 12-word deep,
16-bit audio/telecom receive FIFOs. As in the previous section, the following description refers to
the audio codec for brevity; however, all concepts apply to the telecom portion as well.
For each incoming data frame, if the audio data valid bit is set, the 16-bit audio A/D sample is
extracted and placed in the audio receive FIFO. Nevertheless, note that the MCP also supports a
mode in which the audio data valid bits are ignored, and a number of the incoming frame samples
are not stored in the receive FIFOs. For instance, this may happen after the first sample (of an
incoming frame sequence) is saved to the FIFO, and the MCP’s audio sample rate counter is used to
determine when a new A/D sample has been taken and is available within the incoming frame. Audio
data is transferred from the incoming data frames to the received FIFO only if the audio enable bit is
set within the MCP’s status register. A set of input and sample counter value conditions determine
whether the audio enable bits are 1 or 0.
The MCP’s audio sample rate counters are used to trigger when new D/A conversions are to be
transmitted to the codec. The user should take care in ensuring sample rate counters in the MCP are
synchronized with the respective sample rate counters in the codec, as described previously. When
the audio enable status bit transitions from a 0 to a 1 within the MCP status register, the next available
entry of data is taken from the audio transmit FIFO and is placed within the correct field in the MCP’s
serial shifter. This value is then continuously transferred by the MCP in each data frame to the codec.
The codec only uses the value when its audio sample rate counter decrements to zero. After the audio
D/A conversion is made, both the codec and the MCP’s audio sample rate counters reload with their
modulus value. This reload triggers the audio transmit FIFO to transfer the next available entry of
data to the MCP’s serial shifter. Again, this value is continuously transmitted to the codec in each
data frame until it is used in the next audio D-to-A conversion.
The width of the audio and telecom FIFOs is 16 bits. However, in the UCB1100 the audio codec’s
sample/conversion data size is 12 bits and the telecom is 14 bits. Samples are left justified within the
16-bit audio and telecom data fields in the MCP frame, as well as within the transmit and receive
DS352PP3
JUL 2001
57
Functional Description