EP7211 Datasheet, PDF (117/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.16.1.4 A/D Sampling Mode (ADM)
The A/D sampling mode (ADM) bit selects whether the MCP takes audio and telecom data from the
incoming frame only when their respective data valid bits are set or whenever the MCP’s audio and
telecom sample rate counters time-out, indicating that the data in the next incoming frame is valid.
When ADM = 0, data is taken from the incoming frame and is placed into the audio or telecom FIFO
whenever the incoming audio or telecom data valid bit is set. When ADM = 1, after the MCP is
enabled, data is taken from the incoming frame when the data valid bit is set for the first time. After
this point, the data valid bit is ignored, and samples are stored each time the audio or telecom sample
rate counters decrement to zero. This indicates that a new A/D sample was taken and will be available
in the next frame.
The UCB1100 has two different modes of operation to control the setting of the audio and telecom
data valid bits. In one mode, the codec only sets the data valid bit when a new A/D sample is
contained within the incoming data frame. Once the data is transmitted to the MCP within a receive
data frame, the data valid bit is reset to zero for subsequent data frames until a new A/D sample is
triggered and transmitted to the MCP. In this mode, the user should program ADM = 0. In the other
mode, the data valid bit is set once when the first A/D conversion is made and is placed in the receive
data frame. However, the data valid bit remains set and the MCP cannot determine when samples are
available within the incoming frame. Programming ADM = 1 prevents multiple copies of the sample
to be placed in the FIFO, only storing samples when the sample rate counter times-out.
5.16.1.5 MCP Interrupt Generation
The MCP can generate four maskable interrupts and four non-maskable interrupts, as described in
the sections below. Only one interrupt line is wired into the interrupt controller for the whole MCP.
This interrupt is the wired OR of all eight interrupts (after masking where appropriate). The software
servicing the interrupts must read the status register in the MCP to determine which source(s) caused
the interrupt. It is possible to prevent any MCP sources causing an interrupt by masking the MCP
interrupt in the interrupt controller register.
5.16.1.6 Telecom Transmit FIFO Interrupt Mask (TTM)
The telecom transmit FIFO interrupt mask (TTM) bit is used to mask or enable the telecom transmit
FIFO service request interrupt. When TTM = 0, the interrupt is masked and the state of the telecom
transmit FIFO service request (TTS) bit within the MCP status register is ignored by the interrupt
controller. When TTM = 1, the interrupt is enabled and whenever TTS is set (one) an interrupt
request is made to the interrupt controller. Note that programming TTM = 0 does not affect the
current state of TTS or the telecom transmit FIFO logic’s ability to set and clear TTS; it only blocks
the generation of the interrupt request.
5.16.1.7 Telecom Receive FIFO Interrupt Mask (TRM)
The telecom receive FIFO interrupt mask (TRM) bit is used to mask or enable the telecom receive
FIFO service request interrupt. When TRM = 0, the interrupt is masked and the state of the telecom
receive FIFO service request (TRS) bit within the MCP status register is ignored by the interrupt
DS352PP3
JUL 2001
117
Register Descriptions