EP7211 Datasheet, PDF (45/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
be de-asserted and the main bus will be released so that DMA transfers to the LCD controller can
continue in the background.
The EP7211 will re-arbitrate for control of the bus when the PRDY signal is reasserted to indicate
that the read or write transaction can be completed. The CPU will always be stalled until the PC Card
access is completed.
A card read operation may be split into a request cycle and a data cycle, or it may be combined into
a single request/data transfer cycle. This depends on whether the data requested from the card is
available in the prefetch buffer (internal to the CL-PS6700).
The request portion of the cycle, for a card read, is similar to the request phase for a card write
(described above). If the requested data is available in the prefetch buffer, the CL-PS6700 asserts the
PRDY signal before the rising edge of the third clock and the EP7211 continues the cycle to read the
data. Otherwise, the PRDY signal is de-asserted and the request cycle is stalled. The EP7211 may
then allow the DMA address generator to gain control of the bus, to allow LCD refreshes to continue.
When the CL-PS6700 is ready with the data, it asserts the PRDY signal. The EP7211 then arbitrates
for the bus and, once the request is granted, the suspended read cycle is resumed. The EP7211
resumes the cycle by asserting the appropriate chip select, and data is transferred on the next two
clocks if a word read (one clock if a byte read).
There is no support within the EP7211 for detecting time-outs. The CL-PS6700 device must be
programmed to force the cycle to be completed (with invalid data for a read) and generate an
interrupt if a read or write access is timed out (i.e., RD_FAIL or WR_FAIL interrupt). The system
software can then determine which access was not successfully completed by reading status registers
within the CL-PS6700.
The CL-PS6700 has support for DMA data transfers. However, DMA is supported only by software
emulation because the DMA address generator built into the EP7211 is dedicated to the LCD
controller interface. If DMA is enabled within the CL-PS6700, it will assert its PDREQ signal to
make a DMA request. This can be connected to one of the EP7211’s external interrupts and be used
to interrupt the CPU so that the software can service the DMA request under program control.
Each of the CL-PS6700 devices can generate an interrupt PIRQ. The PIRQ output is open drain on
the CL-PS6700 devices, so if there are two CL-PS6700 devices they may be wire OR’ed to the same
interrupt which can be connected to one of the EP7211’s active low external interrupt sources. On
the receipt of an interrupt, the CPU can read the interrupt status registers on the CL-PS6700 devices
to determine the cause of the interrupt.
All transactions are synchronized to the EXPCLK output from the EP7211 in 18.432 MHz mode or
the external 13 MHz clock. The EXPCLK should be permanently enabled, by setting the EXCKEN
bit in the SYSCON1 register, when the CL-PS6700 is used. The reason for this is that the PC Card
interface and CL-PS6700 internal write buffers need to be clocked after the EP7211 has completed
its bus cycles.
A GPIO signal from the EP7211 can be connected to the PSLEEP pin of the CL-PS6700 devices to
allow them to be put into a power saving state before the EP7211 enters the Standby State. It is
DS352PP3
JUL 2001
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Functional Description