EP7211 Datasheet, PDF (36/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
13-MHZ INPUT
3.6864 MHZ
32.768 KHZ
POR, RUN,
RESET, WAKEUP
BATOK, EXTPWR
PWRFL, BATCHG
EINT[1–3], FIQ,
MEDCHG
FLASHING LED DRIVE
PORTS A, B, D (8-BIT)
PORT E (3-BIT)
KEYBD DRIVERS (0–7)
BUZZER DRIVE
DC-TO-DC
ADCCLK, ADCIN,
ADCOUT, SMPCLK,
ADCCS
SSICLK, SSITXFR,
SSITXDA, SSIRXDA,
SSIRSFR
PLL
32.768-KHZ
OSCILLATOR
STATE CONTROL
POWER
MANAGEMENT
INTERRUPT
CONTROLLER
RTC
GPIO
PWM
SSI1 (ADC)
MULTIMEDIA
CODEC PORT
SSI2
CODEC
ARM720T
ARM7TDMI
CPU CORE
8-KBYTE
CACHE
MMU
WRITE
BUFFER
TIMER
COUNTERS (2)
ON-CHIP
BOOT ROM
INTERNAL DATA BUS
MEMORY CONTROL BLOCK
CL-PS6700
INTFC.
EXPANSION
CONTROL
DRAM
CONTROLLER
INTERNAL ADDRESS BUS
LCD DMA
ICE-JTAG
LCD
CONTROLLER
ON-CHIP SRAM
37.5 KBYTES
IrDA
APB BRIDGE
APB BUS
UART1
UART2
Figure 3-1. EP7211 Block Diagram
D0–D31
PB[0–1], CS[4–5]
EXPCLK, WORD,
CS[0–3], EXPRDY,
WRITE
MOE, MWE,
RAS[0–1], CAS[0–3]
A[0–27],
DRA[0–12]
TEST AND
DEVELOPMENT
LCD DRIVE
LED AND
PHOTODIODE
ASYNC
INTERFACE 1
ASYNC
INTERFACE 2
TM
3.2 CPU Core
The ARM7TDMI core CPU is a 32-bit RISC processor, which is connected directly to the 8-kbyte
unified cache. This cache has 512 lines of 4 words, arranged as a 4-way set associative cache. The
cache is directly connected to the ARM7TDMI CPU, and therefore caches the virtual address from
the CPU. The MMU translates the virtual address into a physical address, it contains a 64-entry
translation look aside buffer (TLB) and is post cache; that is, it only translates external memory
references (cache misses) to save power.
The ARM7TDMI CPU, the MMU, the cache, and the write buffer together make up what is called
the ARM720T processor. See the ARM720T Datasheet for a complete description of the various
logic blocks that make up the processor, as well as all internal register information.
3.3 Interrupt Controller
The ARM720T has two interrupt types: interrupt request (IRQ) and fast interrupt request (FIQ). The
interrupt controller in the EP7211 controls interrupts from 22 different sources. Seventeen interrupt
sources are mapped to the IRQ input and five sources to the FIQ input. FIQs have a higher priority
36
Functional Description
DS352PP3
JUL 2001