EP7211 Datasheet, PDF (86/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
The system control register is a 21-bit read/write register which controls all the general configuration
of the EP7211, as well as modes etc. for peripheral devices. All bits in this register are cleared by a
system reset. The bits in the system control register SYSCON1 are defined below.
Bit
0:3
Description
Keyboard scan: This 4-bit field defines the state of the keyboard column drives. The following table
defines these states.
Keyboard Scan
0
1
2–7
8
9
10
11
12
13
14
15
Column
All driven high
All driven low
All high impedance (tristate)
Column 0 only driven high all others high impedance
Column 1 only driven high all others high impedance
Column 2 only driven high all others high impedance
Column 3 only driven high all others high impedance
Column 4 only driven high all others high impedance
Column 5 only driven high all others high impedance
Column 6 only driven high all others high impedance
Column 7 only driven high all others high impedance
4
TC1M: Timer counter 1 mode. Setting this bit sets TC1 to prescale mode, clearing it sets free running
mode.
5
TC1S: Timer counter 1 clock source. Setting this bit sets the TC1 clock source to 512 kHz, clearing it sets
the clock source to 2 kHz.
6
TC2M: Timer counter 2 mode. Setting this bit sets TC2 to prescale mode, clearing it sets free running
mode.
7
TC2S: Timer counter 2 clock source. Setting this bit sets the TC2 clock source to 512 kHz, clearing it sets
the clock source to 2 kHz.
8
UART1EN: Internal UART enable bit. Setting this bit enables the internal UART.
9
BZTOG: Bit to drive (i.e., toggle) the buzzer output directly when software mode of operation is selected
(i.e., bit BZMOD = 0). See the BZMOD and BUZFREQ bits for more details.
10
BZMOD: This bit selects the buzzer drive mode. When BZMOD = 0, the buzzer drive output pin is con-
nected directly to the BZTOG bit. This is the software mode. When BZMOD = 1, the buzzer drive is in the
hardware mode. Two hardware sources are available to drive the pin. They are the TC1 or a fixed inter-
nally generated clock source. The selection of which source is used to drive the pin is determined by the
state of the BUZFREQ bit in the SYSCON2 register. If the TC1 is selected, then the buzzer output pin is
connected to the TC1 under flow bit. The buzzer output pin changes every time the timer wraps around.
The frequency depends on what was programmed into the timer. See the description of the BUZFREQ
and BZTOG bits for more details.
86
Register Descriptions
DS352PP3
JUL 2001