EP7211 Datasheet, PDF(50/166 Page) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

EP7211 Datasheet, PDF (50/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

◁

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

3.8 Serial Interfaces

The EP7211 offers the following serial interfaces in addition to the two UARTs.

Table 3-12. Serial Interface Options

Type

SPI/Microwire 1

SPI/Microwire 2

MCP Interface

Codec Interface

Comments

Master mode only

Master/slave mode

Touchscreen, codecs, and GPIO

Only for use in the PLL clock mode

Referred To As

ADC Interface

SSI2 Interface

MCP Interface

Codec Interface

Max. Transfer Speed

128 Kbps

512 Kbps

9.216 Mbps

64 Kbps

The inputs/outputs of three of the serial synchronous interfaces (MCP, codec, and SSI2) are

multiplexed onto a single set of external interface pins. If the MCPSEL bit of SYSCON3 is low, then

either SSI2 or the codec interface will be selected to connect to the external pins. When Bit 0 of

SYSCON2 (SERSEL) is high, then the codec is connected to the external pins, when low the

master/slave SSI2 is connected to these pins. When the MCPSEL bit is set high, the MCP interface

is connected to the external pins. On power up, both the MCPSEL and SERSEL bits are reset low,

thus the master/slave SSI2 will be connected to these pins (and configured for slave mode operation

to avoid external drive clashes).

The following table contains pin definition information for the three multiplexed interfaces.

NOTE: The internal names given to each of the three interfaces are unique to help differentiate them from

each other. The sections below that describe each of the three interfaces will use their respective

unique internal pin names for clarity.

Table 3-13. Serial-Pin Assignments

Pin No. External

LQFP Pin Name

SSICCLK

SSITXFR

SSITXDA

SSIRXDA

SSIRXFR

SSI2

Slave Mode

(Internal Name)

SSICCLK = serial

bit clock; Input

SSKTXFR = TX

frame sync; Input

SSITXDA = TX

data; Output

SSIRXDA = RX

data; Input

SSIRXFR = RX

frame sync; Input

SSI2

Master Mode

Output

Input

Output

Codec

Internal Name

PCMCLK =

Output

PCMSYNC =

Output

PCMOUT =

Output

PCMIN = Input

p/u*

MCP

Internal Name

Strength

SIBCLK =

Output

SIBSYNC =

Output

SIBDOUT =

Output

SIBDIN = Input

p/u*

* p/u = use an 10 k pull-up

Functional Description

DS352PP3

JUL 2001

▷