EP7211 Datasheet, PDF (106/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.9.2 UBRLCR1–2 UART1–2 Bit Rate and Line Control Registers
ADDRESS: 0x8000.04C0 and 0x8000.14C0
31:19
18:17
WRDLEN
16
FIFOEN
15
XSTOP
14
EVENPRT
13
PRTEN
12
BREAK
11:0
Bit rate
divisor
The bit rate divisor and line control register is a 19-bit read / write register. Writing to these registers
sets the bit rate and mode of operation for the internal UARTs.
Bit
0:11
Description
Bit rate divisor: This 12-bit field sets the bit rate. If the system is operating from the PLL clock, then the bit
rate divider is fed by a clock frequency of 3.6864 MHz, which is then further divided internally by 16 to give
the bit rate. The formula to give the divisor value for any bit rate when operating from the PLL clock is: Divi-
sor = (230400/bit rate divisor) – 1. A value of zero in this field is illegal when running from the PLL clock.
The tables below show some example bit rates with the corresponding divisor value. In 13 MHz mode, the
clock frequency fed to the UART is 1.8571 MHz. In this mode, zero is a legal divisor value, and will gener-
ate the maximum possible bit rate. The tables below show the bit rates available for both 18.432 MHz and
13 MHz operation.
Table 5-10. UART Bit Rates Running
from the PLL Clock
Table 5-11. UART Bit Rates Running
from an External 13.0 MHz Clock
Divisor Value
0
1
2
3
5
11
15
23
95
191
2094
Bit Rate Running
From the Pll Clock
—
115200
76800
57600
38400
19200
14400
9600
2400
1200
110
Divisor
Value
0
1
2
5
7
11
47
96
1054
Bit Rate at
13 Mhz
116071
58036
38690
19345
14509
9673
2418
1196
110.02
Error on
13 Mhz Value
0.75%
0.75%
0.75%
0.75%
0.75%
0.75%
0.42%
0.28%
0.18%
12
BREAK: Setting this bit will drive the TX output active (high) to generate a break.
13
PRTEN: Parity enable bit. Setting this bit enables parity detection and generation
106
Register Descriptions
DS352PP3
JUL 2001